CY24488 datasheet(9/15 Pages) CYPRESS

9 / 15 page

CY24488

Document #: 001-09608 Rev. *A

Page 9 of 15

Figure 3. Data Transfer Sequence on the Serial Bus

Figure 4. Data Frame Architecture

Figure 5. Data Valid and Data Transition Periods

SCL

START

Condition

SDAT

STOP

Data may

Address or

Acknowledge

Valid

be changed

Condition

SDAT Write

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK

Slave

1 Bit

ACK

8-bit

Data

Stop Signal

Multiple

Contiguous

Registers

Slave

1 Bit

ACK

8-bit

Data

(XXH)

(XXH+1)

Slave

1 Bit

ACK

8-bit

Data

(XXH+2)

Slave

1 Bit

ACK

8-bit

Data

(FFH)

Slave

1 Bit

ACK

8-bit

Data

(00H)

Slave

1 Bit

ACK

Slave

1 Bit

ACK

SDAT Read

Start Signal

Device

Address

7-bit

R/W = 1

1 Bit

8-bit

Data

Slave

1 Bit

ACK

Slave

1 Bit

ACK

Stop Signal

SDAT Read

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK

Slave

1 Bit

ACK

7-bit

Device

Stop Signal

Multiple

Contiguous

Registers

Master

1 Bit

ACK

8-bit

Data

Master

1 Bit

ACK

(XXH)

Master

1 Bit

ACK

8-bit

Data

(XXH+1)

Master

1 Bit

ACK

8-bit

Data

(FFH)

Master

1 Bit

ACK

8-bit

Data

(00H)

Master

1 Bit

ACK

Master

1 Bit

ACK

Current

Address

Read

Address

+R/W=1

Repeated

Start bit

SDAT

SCLK

Data Valid

Transition

to next Bit

CLKLOW

CLKHIGH

VIH

VIL

tSU

tDH

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