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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ADIN1110BCPZ-R7 Folha de dados(PDF) 79 Page - Analog Devices |
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ADIN1110BCPZ-R7 Folha de dados(HTML) 79 Page - Analog Devices |
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79 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 79 of 107 Table 134. Bit Descriptions for B10L_PMA_STAT (Continued) Bits Bit Name Description Reset Access [9:0] RESERVED Reserved. 0x0 R 10BASE-T1L Test Mode Control Register Device Address: 0x01; Register Address: 0x08F8, Reset: 0x0000, Name: B10L_TEST_MODE_CNTRL This address corresponds to the 10BASE-T1L PMA test mode control register specified in Clause 45.2.1.186c of Standard 802.3cg. The default value of this register selects normal operation without management intervention as the initial state of the device. Table 135. Bit Descriptions for B10L_TEST_MODE_CNTRL Bits Bit Name Description Reset Access [15:13] B10L_TX_TEST_MODE 10BASE-T1L Transmitter Test Mode. 0x0 R/W 000: normal operation. 001: Test Mode 1—transmitter output voltage and timing jitter test mode. When Test Mode 1 is enabled, the PHY repeatedly transmits the data symbol sequence (+1, −1). 010: Test Mode 2—transmitter output droop test mode. When Test Mode 2 is enabled, the PHY transmits ten +1 symbols followed by ten −1 symbols. 011: Test Mode 3—normal operation in idle mode. When Test Mode 3 is enabled, the PHY transmits as in nontest operation and in the master data mode with data set to normal interframe idle signals. [12:0] RESERVED Reserved. 0x0 R Frequency Offset Saturation Threshold for CR Stability Check Register Device Address: 0x01; Register Address: 0x8015, Reset: 0x0008, Name: CR_STBL_CHK_FOFFS_SAT_THR Table 136. Bit Descriptions for CR_STBL_CHK_FOFFS_SAT_THR Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. 0x0 R [10:0] CR_STBL_CHK_FOFFS_SAT_THR Frequency Offset Saturation Threshold for Clock Recovery (CR) Stability Check. 0x8 R/W Slave IIR Filter Change Echo Acquisition Clock Recovery Proportional Gain Register Device Address: 0x01; Register Address: 0x81E7, Reset: 0x0400, Name: SLV_FLTR_ECHO_ACQ_CR_KP Table 137. Bit Descriptions for SLV_FLTR_ECHO_ACQ_CR_KP Bits Bit Name Description Reset Access [15:0] SLV_FLTR_ECHO_ACQ_CR_KP Slave Infinite Impulse Response (IIR) Filter Change Echo Acquisition Clock Recovery Proportional Gain. 0x400 R/W 10BASE-T1L PMA Link Status Register Device Address: 0x01; Register Address: 0x8302, Reset: 0x0000, Name: B10L_PMA_LINK_STAT This address can be read to determine the 10BASE-T1L PMA link status. Reading B10L_PMA_LINK_STAT clears the latching condition of these bits. Table 138. Bit Descriptions for B10L_PMA_LINK_STAT Bits Bit Name Description Reset Access [15:10] RESERVED Reserved. 0x0 R |
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