ADIN1110BCPZ-R7 datasheet(53/107 Pages) AD

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Data Sheet

ADIN1110

REGISTERS

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Rev. B | 53 of 107

Table 48. Bit Descriptions for IMASK0 (Continued)

Bits

Bit Name

Description

Reset

Access

HDREM

Header Error Mask. Setting this bit to 1 prevents the header error (HDRE) status bit in STATUS0 from

asserting the footer EXST bit. This field is only used with the OPEN Alliance SPI protocol.

0x1

R/W

LOFEM

Loss of Frame Error Mask. Setting this bit to 1 prevents the loss of the frame error (LOFE) status bit in

STATUS0 from asserting the footer EXST bit.

0x1

R/W

RXBOEM

Receive Buffer Overflow Error Mask. Setting this bit to 1 prevents the receive buffer overflow error (RXBOE)

status bit in STATUS0 from asserting the footer EXST bit.

0x1

R/W

TXBUEM

Transmit Buffer Underflow Error Mask. Setting this bit to 1 prevents the transmit buffer underflow error

(TXBUE) status bit in STATUS0 from asserting the footer EXST bit.

0x1

R/W

TXBOEM

Transmit Buffer Overflow Error Mask. Setting this bit to 1 prevents the transmit buffer overflow error (TXBOE)

status bit in STATUS0 from asserting the footer EXST bit.

0x1

R/W

TXPEM

Transmit Protocol Error Mask. Setting this bit to 1 prevents the transmit protocol error (TXPE) status bit in

STATUS0 from asserting IRQn.

0x1

R/W

Mask Bits for Driving the Interrupt Pin Register

Address: 0x0D, Reset: 0x43FA1F1A, Name: IMASK1

Table 49. Bit Descriptions for IMASK1

Bits

Bit Name

Description

Reset

Access

[31:13]

RESERVED

Reserved.

0x21FD0

TX_ECC_ERR_MASK

Mask Bit for TXF_ECC_ERR.

0x1

R/W

RX_ECC_ERR_MASK

Mask Bit for RXF_ECC_ERR.

0x1

R/W

SPI_ERR_MASK

Mask Bit for SPI_ERR. This field is only used with the generic SPI protocol.

0x1

R/W

RESERVED

Reserved.

0x1

R/W

P1_RX_IFG_ERR_MASK

Mask Bit for RX_IFG_ERR.

0x1

R/W

[7:5]

RESERVED

Reserved.

0x0

P1_RX_RDY_MASK

Mask Bit for P1_RX_RDY. This field is only used with the generic SPI protocol.

0x1

R/W

TX_RDY_MASK

Mask Bit for TX_FRM_DONE. This field is only used with the generic SPI protocol.

0x1

R/W

RESERVED

Reserved.

0x0

LINK_CHANGE_MASK

Mask Bit for LINK_CHANGE.

0x1

R/W

RESERVED

Reserved.

0x0

Transmit Time Stamp Capture Register A (High)

Address: 0x10, Reset: 0x00000000, Name: TTSCAH

This field contains the upper 32 bits of the captured time stamp for when the requested frame was transmitted.

Table 50. Bit Descriptions for TTSCAH

Bits

Bit Name

Description

Reset

Access

[31:0]

TTSCH_A

Transmit Time Stamp A. Bits[63:32].

0x0

Transmit Time Stamp Capture Register A (Low)

Address: 0x11, Reset: 0x00000000, Name: TTSCAL

This field contains the lower 32 bits of the captured time stamp for when the requested frame was transmitted.

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