DSP56362P datasheet(40/152 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56362 Technical Data, Rev. 4

3-14

Freescale Semiconductor

3.10

External Memory Expansion Port (Port A)

3.10.1

SRAM Timing

Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1

No.

Characteristics

Symbol

Expression2

100 MHz

120 MHz

Unit

Min

Max

Min

Max

100 Address valid and AA assertion pulse width3

tRC, tWC

(WS + 1)

× T

C − 4.0

≤ WS ≤ 3]

16.0

—

12.0

—

(WS + 2)

× T

C − 4.0

≤ WS ≤ 7]

56.0

—

46.0

—

(WS + 3)

× T

C − 4.0

[WS

≥ 8]

106.0

—

87.0

—

101 Address and AA valid to WR assertion

tAS

100 MHz:

0.25

× T

C − 2.0

[WS = 1]

0.5

—

0.1

—

1.25

× T

C − 2.0

[WS

≥ 4]

10.5

—

8.4

—

102 WR assertion pulse width

tWP

100 MHz:

1.5

× T

C − 4.0

[WS = 1]

11.0

—

8.5

—

All frequencies:

× T

C − 4.0

≤ WS ≤ 3]

16.0

—

12.7

—

(WS

− 0.5) × T

C − 4.0

[WS

≥ 4]

31.0

---

25.2

—

103 WR deassertion to address not valid

tWR

100 MHz:

0.25

× T

C − 2.0

≤ WS ≤ 3]

0.5

—

0.1

—

1.25

× T

C − 2.0

≤ WS ≤ 7]

10.5

—

8.4

—

2.25

× T

C − 2.0

[WS

≥ 8]

20.5

—

16.7

—

All frequencies:

1.25

× T

C − 4.0

≤ WS ≤ 7]

8.5

—

6.4

—

2.25

× T

C − 4.0

[WS

≥ 8]

18.5

—

14.7

—

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