Overview

Freescale Semiconductor, Inc. designed the DSP56362 to support digital audio applications requiring digital audio compression and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56362 usesthe high performance,

single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Symphony™ DSP family, as shown in Figure 1-1. This design provides a two-fold performance increase over Freescale’s popular Symphony family of DSPs while retaining code compatibility. Significant

architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V.

Features

• Multimode, multichannel decoder software functionality

— Dolby Digital and Pro Logic

— MPEG2 5.1

—DTS

— Bass management

• Digital audio post-processing capabilities

— 3D Virtual surround sound

— Lucasfilm THX5.1

— Soundfield processing

— Equalization

• Digital Signal Processing Core

— 100 MIPS with a 100 MHz clock at 3.3 V +/- 5%

— Object code compatible with the DSP56000 core

— Highly parallel instruction set

— Data arithmetic logic unit (ALU)

– Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)

– 56-bit parallel barrel shifter (fast shift and normalization;bit stream generation and parsing)

– Conditional ALU instructions

– 24-bit or 16-bit arithmetic support under software control

— Program control unit (PCU)

– Position independent code (PIC) support

– Addressing modes optimized for DSP applications (including immediate offsets)

– On-chip instruction cache controller

– On-chip memory-expandable hardware stack

– Nested hardware DO loops

– Fast auto-return interrupts

— Direct memory access (DMA)

– Six DMA channels supporting internal and external accesses

– One-, two-, and three- dimensional transfers (including circular buffering)

– End-of-block-transfer interrupts

– Triggering from interrupt lines and all peripherals

— Phase-locked loop (PLL)

– Software programmable PLL-based frequency synthesizer for the core clock

– Allows change of low-power divide factor (DF) without loss of lock

– Output clock with skew elimination

— Hardware debugging support

– On-Chip Emulation (OnCE‘) module

– Joint Action Test Group (JTAG) test access port (TAP)

– Address trace mode reflects internal program RAM accesses at the external port