1998 Mar 17

3

Philips Semiconductors

Product specification

7 N-channel 80 m

Ω FET array

enhancement mode MOS transistors

PHN708

QUICK REFERENCE DATA

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

2. Pulse width and duty cycle limited by maximum junction temperature.

3. When only one FET dissipates.

4. When either combination of FETs 1-5, 1-6, 2-5, 2-7, 3-6 or 3-7 dissipate an equal amount of power.

5. When FET four plus either combination of FETs 1-5, 1-6, 2-5, 2-7, 3-6 or 3-7 dissipate an equal amount of power.

6. When all seven FETs dissipate an equal amount of power.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

drain-source voltage (DC)

−

30

V

gate-source voltage (DC)

−±20

V

gate-source threshold voltage

1

2.8

V

drain current (DC)

−

3.1

A

drain-source on-state resistance

−

80

m

Ω

total power dissipation

−

1.3

W

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

Per FET

drain-source voltage (DC)

−

30

V

gate-source voltage (DC)

−±20

V

drain current (DC)

−

3.1

A

peak drain current

note 2

−

12.4

A

total power dissipation

−

1.3

W

−

1.13

W

−

0.92

W

−

0.77

W

storage temperature

−55

+150

°C

operating junction temperature

−55

+150

°C

Source-drain diode

source current (DC)

−

1.3

A

peak source current

note 2

−

5.2

A