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AS8579

Datasheet

• PUBLIC

DS000707

• v4-01 • 2022-Jun-08

│ 28

Figure 27:

EDIV Register

EDIV [3:0] Binary

Read/Write

CLK_E Frequency

Dividing Factor

0000

R/W

0001

R/W

0010

R/W

0011

R/W

0100

R/W

0101

R/W

0110

R/W

0111

R/W

1000

R/W

1001

R/W

1010

R/W

1011

R/W

1100

R/W

1101

R/W

1110

R/W

1111

R/W

The clock obtained by the frequency division of the CLK is called MCLK and is used to clock all the

digital part except the SPI interface. Each time there is an EDIV change, an automatic OTP reset is

generated to clean up the memory from possible timing error if the previous selected MCLK was

higher than 4 MHz. The reload of the OTP memory takes less than 8190 MCLK clock cycles, during

the reload phase it is possible to have SPI communication, but not possible to start sensing.

7.2.7

Frequency Selection Register (Address 0x21/0x31)

The 0x31 command is used to select the sine wave generator frequency for the sensor driver output.

At power-up, FREQ default is set to 0x00. The 0x21 command is used to read the current value of

FREQ.

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