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AS8579

Functional Description

Datasheet

• PUBLIC

DS000707

• v4-01 • 2022-Jun-08

│ 22

ADC Functional Description

For digitizing the I and Q values, a 10-bit ADC is used. Conversions are run using the internal system

clock.

The ADC can do different conversion modes. This can be set in the ADCTL register (0x2A/0x3A).

(see 7.2.16)

Single Conversion

“Single Conversion” causes the ADC to wait for the “system settling time" before starting sampling and

then to accumulate the number of samples, specified in the register ADCTL [5:4]. I and Q samples

arrive interleaved. The DSP control logic will provide the analog part the signal IQMUX to switch the

ADC analog input between I channel and Q channel.

Once completed, I and Q results are moved to the SPI output registers and the “ADC_COMPLETE” bit

in register 0x05 is set. Before another “Single Conversion” can be started, the ADC must be reset by

either performing a Quick Read (0x90), or by issuing the “ADC Reset” command.

Figure 18:

Measuring Cycle

Continuous Conversion

“Continuous Conversion” mode causes the ADC to take successive samples accumulations of I and

Q, again the number of samples taken is specified by ADCTL [5:4] register (0x2A/0x3A).

The ADC is time multiplexed between the I and Q channels (I and Q samples are interleaved). Each

data point stored to the SPI output register is the accumulation of a programmed number of 10-bit

ADC values, for each I and Q. Data is stored to the SPI as a complete I and Q set (data synchronicity

is guaranteed by the Control Logic).

Set-up

ADCGO

Settling phase I and Q

Sampling phase

400

352

ADC_COMPLETE

ADC sampling period:

Tsample=ADCLK*11

Sampling phase:

TsampPH=Tsample*8

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