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AS7343 Folha de dados(PDF) 38 Page - OSRAM GmbH |
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AS7343 Folha de dados(HTML) 38 Page - OSRAM GmbH |
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38 / 58 page ![]() Document Feedback AS7343 Register Description Datasheet • PUBLIC DS001046 • v6-00 • 2023-Jun-07 57 │ 37 Addr: 0x66 CFG12 Bit Bit Name Default Access Bit Description 3 CH3 4 CH4 5 CH5 10.2.6 Device Status Registers The following registers provide status of the device and indicate details about saturation, interrupts, over temperature, device execution and ambient light flicker detection. STATUS Register (Address 0x93) The primary status register for AS7343 indicates if there are saturation or interrupt events that need to be handled by the user. This register is self- clearing, meaning that writing a “1” to any bit in the register clears that status bit. In this way, the user should read the STATUS register, handle all indicated event(s) and then write the register value back to STATUS to clear the handled events. Writing “0” will not clear those bits if they have a value of “1”, which means that new events that occurred since the last read of the STATUS register will not be accidentally cleared. In case channel saturation has happened (ASAT or FDSAT), it is recommended to discard the measurement results and re-configure device configuration such as AGAIN and Integration Time to avoid saturation. Figure 44: STATUS Register Addr: 0x93 STATUS Bit Bit Name Default Access Bit Description 7 ASAT 0 R, SC Spectral and Flicker Detect Saturation. If ASIEN is set, indicates Spectral saturation. Check STATUS 2 register to distinguish between analog or digital saturation. 6:4 Reserved 0 R Reserved 3 AINT 0 R, SC Spectral Channel Interrupt. If SP_IEN is set, indicates that a spectral event that met the programmed thresholds and persistence (APERS) occurred. 2 FINT 0 R, SC FIFO Buffer Interrupt. If FIEN is set, indicates that the FIFO_LVL fulfills the threshold condition. If cleared by writing 1, the interrupt will be asserted again as more data is collected. To fully clear this interrupt, all data must be read from the FIFO buffer. 1 Reserved 0 R Reserved 0 SINT 0 R, SC System Interrupt. |
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