AM263P4 datasheet(92/154 Pages) TI

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RGMII[x] RD 3

[ :0]

(B)

RGMII[x] RX_CTL

(B)

RGMII[x] RXC

(A)

RGMII4

RXERR

RXDV

2nd Half-byte

1st Half-byte

RGMII2

RGMII3

RGMII1

RGMII5

RGMII[x]_RXC must be externally delayed relative to the data and control pins.

Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of

RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of

RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.

Figure 6-9. CPSW RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII

Mode

6.11.5.1.2.4 CPSW RGMII[x]_TCLK Switching Characteristics - RGMII Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

RGMII6

tc(TXC)

Cycle time, TXC

10Mbps

360

440

100Mbps

1000Mbps

7.2

8.8

RGMII7

tw(TXCH)

Pulse duration, TXC high

10Mbps

160

240

100Mbps

1000Mbps

3.6

4.4

RGMII8

tw(TXCL)

Pulse duration, TXC low

10Mbps

160

240

100Mbps

1000Mbps

3.6

4.4

6.11.5.1.2.5 CPSW RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

RGMII9

tosu(TD-TXC)

Output setup time, RGMII[x]_TD[3:0] valid

to RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

tosu(TX_CTL-TXC)

Output setup time, RGMII[x]_TX_CTL valid

to RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

RGMII10

toh(TXC-TD)

Output hold time, RGMII[x]_TD[3:0] valid

after RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

toh(TXC-TX_CTL)

Output hold time, RGMII[x]_TX_CTL valid

after RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.2

TI Information - Selective Disclosure

AM263P4, AM263P2, AM263P1, AM263P4-Q1, AM263P2-Q1, AM263P1-Q1

SPRSP81 – OCTOBER 2023

www.ti.com

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