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AT89C5132-ROTUL Folha de dados(PDF) 50 Page - ATMEL Corporation |
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AT89C5132-ROTUL Folha de dados(HTML) 50 Page - ATMEL Corporation |
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50 / 181 page ![]() 50 4173D–USB–02/06 AT89C5132 Figure 12-1. Timer 0 and Timer 1 Clock Controller and Symbols 12.3 Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 12-2 through Figure 12-8 show the logical configuration of each mode. Timer 0 is controlled by the four lower Bits of TMOD register (see Table 41) and Bits 0, 1, 4 and 5 of TCON register (see Table 40). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (C/T0#) and mode of operation (M10 and M00). TCON register pro- vides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request. It is important to stop Timer/Counter before changing mode. 12.3.1 Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five Bits of TL0 register (see Figure 12-2). The upper three Bits of TL0 register are indeterminate and should be ignored. Prescaler over- flow increments TH0 register. Figure 12-3 gives the overflow period calculation formula. Figure 12-2. Timer/Counter x (x = 0 or 1) in Mode 0 Figure 12-3. Mode 0 Overflow Period Formula PER CLOCK TIM0 CLOCK OSC CLOCK 0 1 T0X2 CKCON.1 ÷ 2 Timer 0 Clock Timer 0 Clock Symbol PER CLOCK TIM1 CLOCK OSC CLOCK 0 1 T1X2 CKCON.2 ÷ 2 Timer 1 Clock Timer 1 Clock Symbol TIMx CLOCK TRx TCON Reg TFx TCON Reg 0 1 GATEx TMOD Reg ÷ 6 Overflow Timer x Interrupt Request C/Tx# TMOD Reg THx (8 Bits) TLx (5 Bits) INTx Tx 6 ⋅ (16384 – (THx, TLx)) TFx PER= F TIMx |
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