Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

Preview PDF HTML

WM8711SEDS/R Folha de dados(PDF) 15 Page - Wolfson Microelectronics plc

Nome de Peças WM8711SEDS/R
Descrição Electrónicos  Internet Audio DAC with Integrated Headphone Amplifier
PDF  47 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  WOLFSON [Wolfson Microelectronics plc]
Página de início  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8711SEDS/R Folha de dados(HTML) 15 Page - Wolfson Microelectronics plc

Back Button WM8711SEDS/R Datasheet HTML 11Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 12Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 13Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 14Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 15Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 16Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 17Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 18Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 19Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 47 page
background image
Production Data
WM8711 / WM8711L
w
PD Rev 4.3 September 2006
15
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
60
ns
SCLK pulse cycle time
tSCY
80
ns
SCLK pulse width low
tSCL
20
ns
SCLK pulse width high
tSCH
20
ns
SDIN to SCLK set-up time
tDSU
20
ns
SCLK to SDIN hold time
tDHO
20
ns
CSB pulse width low
tCSL
20
ns
CSB pulse width high
tCSH
20
ns
CSB rising to SCLK rising
tCSS
20
ns
SDIN
SCLK
t
3
t
1
t
6
t
2
t
7
t
5
t
4
t
3
t
8
t
10
Figure 5 Program Register Input Timing – 2-Wire MPU Interface Timing
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
526
kHz
SCLK Low Pulsewidth
t1
1.3
us
SCLK High Pulsewidth
t2
600
ns
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
ns
SDIN, SCLK Rise Time
t6
300
ns
SDIN, SCLK Fall Time
t7
300
ns
Setup Time (Stop Condition)
t8
600
ns
Data Hold Time
t10
900
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47


Folha de dados Download

Go To PDF Page


Ligação URL



ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   Link para a ficha técnica    |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com