AT80C51RA2-RLSIV datasheet(31/85 Pages) IRF

31 / 85 page

4188E–8051–08/06

AT/TS8xC51Rx2

Figure 6-7.

PCA Compare Mode and PCA Watchdog Timer

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-

wise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur

while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user

software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be

controlled by accessing to CCAPMn register.

6.3.3

High Speed Output Mode

In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a

match occurs between the PCA counter and the module's capture registers. To activate this

mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 6-

8).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

CCAPnH

CCAPnL

ECOMn

CCAPMn, n = 0 to 4

0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFn

CAPPn

16 bit comparator

Match

CCON

0xD8

PCA IT

Enable

PCA counter/timer

RESET *

CIDL

CPS1

CPS0

ECF

CMOD

0xD9

WDTE

* Only for Module 4

Reset

Write to

CCAPnL

Write to

CCAPnH

CCF2

CCF1

CCF0

CCF3

CCF4

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