AT80C51RA2-RLSIV datasheet(18/85 Pages) IRF

18 / 85 page

4188E–8051–08/06

AT/TS8xC51Rx2

address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or

write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)

internal data memory. The stack may not be located in the XRAM.

Figure 6-1.

Internal and External Data Memory Address

Table 6-1.

Auxiliary Register

AUXR

XRAM

256 bytes

Upper

128 bytes

Internal

Ram

Lower

128 bytes

Internal

Ram

Special

Function

FF(RA, RB, RC)/2FF (RD)

External

Data

Memory

0000

0100 (RA, RB, RC) or 0300 (RD)

FFFF

indirect accesses

direct accesses

direct or indirect

accesses

AUXR

Address 08EH

EXTRAM

Reset value

XXX

Symbol

Function

Not implemented, reserved for future use.

(1)

User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0,

and its active value will be 1. The value read from a reserved bit is indeterminate.

Disable/Enable ALE

Operating Mode

ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode

is used)

ALE is active only during a MOVX or MOVC instruction

EXTRAM

Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR

EXTRAM

Operating Mode

Internal XRAM access using MOVX @ Ri/ @ DPTR

External data memory access

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