UPD17708 datasheet(268/358 Pages) RENESAS

268 / 358 page

266

µPD17704, 17705, 17707, 17708, 17709

17.5 PLL Disabled Status

The PLL frequency synthesizer stops (is disabled) while the CE pin is low.

Likewise, it also stops when PLL disabled status is selected by the PLL reference frequency register (RF address

11H).

Table 17-1 shows the operation of each block in the PLL disabled status.

When the VCOL and VCOH pins are disabled by the PLL mode selection register, only the VCOL and VCOH pins

are internally pulled down, and the other blocks operate.

Because the PLL frequency selection register and PLL mode selection register are not initialized at CE reset (hold

the previous status), these registers return to the previous status when the CE pin has gone low, the PLL frequency

synthesizer has been disabled, and then CE pin has gone high.

To disable the PLL frequency synthesizer at CE reset, initialize these registers in software.

At power-ON reset, the PLL frequency synthesizer is disabled.

Table 17-1. Operation of Each Block under Each PLL Disable Condition

Condition

CE Pin = Low Level

CE Pin = High Level

(PLL disabled)

PLL reference frequency

PLL mode selection

selection register = 1111B

Each Block

(PLL disabled)

(VCOH and VCOL disabled)

VCOL, VCOH pins

Internally pulled down

Programmable divider

Division stopped

Operates

Reference frequency generator

Output stopped

Operates

Phase comparator

Output stopped

Operates

Charge pump

Error out pins are floated

Operates.

However, usually outputs

low level because no

signal is input

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