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UPD17708 Folha de dados(PDF) 44 Page - Renesas Technology Corp

Nome de Peças UPD17708
Descrição Electrónicos  MOS INTEGRATED CIRCUIT
PDF  358 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17708 Folha de dados(HTML) 44 Page - Renesas Technology Corp

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µPD17704, 17705, 17707, 17708, 17709
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Table 4-1. Data Memory Manipulation Instructions
Function
Instruction
Operation
Add
ADD
ADDC
Subtract
SUB
SUBC
Logic
AND
OR
XOR
Compare
SKE
SKGE
SKLT
SKNE
Transfer
MOV
LD
ST
Judge
SKT
SKF
4.3 Data Memory Addressing
Figure 4-3 shows address specification of the data memory.
An address of the data memory is specified by a bank, row address, and column address.
A row address and a column address are directly specified by a data memory manipulation instruction.
However, a bank is specified by the contents of a bank register.
For the details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG).
Figure 4-3. Address Specification of Data Memory
Data memory address
Bank register
Column address
Row address
Bank
b3
b2
b1
b0
b2
b1
b0
b3
b2
b1
b0
Instruction operand



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