UPD17708 datasheet(63/358 Pages) RENESAS

63 / 358 page

µPD17704, 17705, 17707, 17708, 17709

Table 7-2. Modification of Data Memory Address and Indirect Transfer Address by Index

BANK

: bank register

: index register

IXE

: index enable flag

IXH

: bits 10 through 8 of index register

IXM

: bits 7 through 4 of index register

IXL

: bits 3 through 0 of index register

: data memory address indicated by mR, mC

: data memory row address (high-order)

: data memory column address (low-order)

: data memory row address pointer

MPE : memory pointer enable flag

: general register column address

: general register pointer

(X)

: contents addressed by X

X: direct address such as “m” and “r”

b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0

General Register Address Specified by “r”

Data Memory Address Specified by “m”

Indirect Transfer Address Specified by “@r”

Bank

Row

address

Column

address

Bank

Row

address

Column

address

Bank

Row

address

Column

address

BANK

(r)

ditto

(r)

ditto

BANK

(r)

ditto

MPE

IXE

IXH, IXM

Logical

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