UPD17708 datasheet(231/358 Pages) RENESAS

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µPD17704, 17705, 17707, 17708, 17709

16.2.8 I2C bus mode

(1) Outline of I2C bus mode

In the I2C bus mode, communication is carried out with two pins, SCL and SDA.

The features of the I2C bus mode are as follows.

•

Communication can be controlled under the start/stop conditions and by the acknowledge signal for the

ninth clock.

•

Communication can be kept waiting by externally fixing the clock to low level with an N-ch open-drain pin.

(2) Timing chart

Figure 16-10 shows the timing chart.

Figure 16-10. Timing Chart in I2C Bus Mode

<1> Initial status (general-purpose input port)

<2> Generates start condition by general-purpose I/O port

<3> Sets transmission status of master

<4> Releases wait

<5> Wait timing when data wait status is set

<6> Wait timing when acknowledge wait status is set

<7> Sets general-purpose I/O port (releases serial operation mode)

<8> Generates stop condition by general-purpose I/O port

<9> Issues interrupt request when value of clock counter first reaches 7 after detection of start condition

<10> Issues interrupt request when value of clock counter reaches 7

<11> Issues interrupt request when value of clock counter reaches 8

<12> Issues interrupt request after stop condition is detected

Clock counter

Serial data

Shift clock

SIO0NWT

SIO0WSTT

SIO0SF8

SIO0SF9

SBSTT

SBBSY

Stop condition

<1>

<2>

<3>

<4>

ACK

789

INT

<9>

<10>

<5>

<11>

<6>

<7>

<8>

<12>

Start condition

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