UPD17708 datasheet(201/358 Pages) RENESAS

201 / 358 page

199

µPD17704, 17705, 17707, 17708, 17709

14.4 Comparison Timing Chart

14.4.1 In software mode

Comparison is completed three instructions after data has been set (by the PUT instruction) to the A/D

converter reference voltage setting register (ADCR).

Figure 14-7 shows the timing chart.

Figure 14-7. Timing Chart of Comparison by A/D Converter

14.4.2 In hardware mode

When the ADCMD flag is set to “1”, A/D conversion is started. The ADCSTT flag is set to “1”, and comparison

is completed after 17 instructions have been executed. At this time, the ADCSTT flag is reset to “0” after 15

instructions have been executed after the ADCMD flag was set to “1”. This is because execution time of two

instructions is required to judge the status of the ADCSTT flag. For details, also refer to 14.5 Using A/D

Converter.

Figure 14-8 shows the timing chart.

Figure 14-8. Timing Chart of Comparison by A/D Converter

Instruction cycle

“0”

PUT ADCR, DBF

Result of comparison

Sample & hold

ADCSTT fiag

ADCCMP fiag

Comparison starts

Instruction cycle

1st

8th

Result of comparison

315

Sample & hold

ADCSTT flag

Reference voltage setting register

A/D converter

ADCMD flag (=1) set.

Comparison starts

End of comparison

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