MA2910
9
As one example, consider the case of a memory search
instruction. As shown, the instruction at microprogram address
63 can be instruction 4 (PUSH), which will push the value 64
onto the microprogram stack and load the number N, which is
one less than the number of memory locations to be searched
before ending the search. Location 64 contains a
microinstruction which fetches the next operand from the
memory area being searched and compares it with the search
key. Location 65 contains a microinstruction which tests the
result of the comparison and is a THREE-WAY BRANCH for
microprogram control. If no match is found, the test fails and
the microprogram goes back to location 64 for the next
operand address.
When the count becomes zero, the microprogram
branches to location 72, and carries out the instruction at
location 72, if no match is found. If a match occurs on any
execution of the THREE-WAY BRANCH at location 65, control
falls through to location 66 which handles the case. Whether
the instruction ends by finding a match or not, the stack will
have been POP’d once thus removing the value 64 from the
top of the stack.
ARCHITECTURE
ONE LEVEL PIPELINE BASED (RECOMMENDED)
One level pipeline provides better speed than most other
architectures as the Microprogram Memory and the MA2901
array are in parallel paths.
This is the recommended architecture for all MA2900
designs.
Figure 19a: One level Pipeline Based
Figure 18: 15 THREE-WAY BRANCH (TWB)
Figure 19b: Timing relationship in the CCU
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