MA2910
8
Instruction 12: Load Counter and Continue.
This instruction simply enables the counter to be loaded
with the value at its parallel inputs. These inputs are normally
connected to the pipeline branch address field which (in the
architecture being described here) serves to supply either a
branch address or a counter value depending upon the
microinstruction being executed.
Altogether there are three ways of loading the counter: the
explicit load by this instruction 12; the conditional load included
as part of instruction 4; and use of RLD input along with any
instructions.
The use of RLD with any instruction overrides any counting
or decrementation specified in the instruction, calling for a load
instead. Its use provides additional microinstruction power, at
the expense of one bit of microinstruction width
Instruction 12 is exactly equivalent to the combination of
instruction 14 and RLD LOW. Its purpose is to provide a simple
capability to load the register/counter in those implementations
which do not provide microprogrammed control for RLD.
The example shows the TEST END-OF-LOOP
microinstruction at address 56. If the test fails, the
microprogram will branch to address 52. Address 52 is on the
stack because a PUSH instruction had been executed at
address 51. If the test is passed at instruction 56, the loop is
terminated and the next sequential microinstruction at address
57 is executed which also causes the stack to be POP’d; thus
accomplishing the required stack maintenance.
Instruction 14: CONTINUE.
This simply causes the microprogram counter to increment
so that the next sequential microinstruction is executed. This is
the simplest microinstruction of all and should be the default
instruction which the firmware requests whenever there is
nothing better to do.
Instruction 15: Three-Way-Branch.
This instruction is the most complex and provides for
testing of both a data-dependent condition and the counter
during one microinstruction and provides for selecting among
one of three microinstruction addresses as the next
microinstruction to be performed. Like instruction 8, a previous
instruction will have loaded a count into the register/counter
while pushing a microbranch address onto the stack.
Instruction 15 performs a decrement-and-branch-until-zero
function similar to instruction 8. The next address is taken from
the top of the stack until the count reaches zero. When the
counter reaches zero the next address comes from the
pipeline register. The above action continues as long as the
test condition fails. If at any execution of instruction 15 the test
condition is passed, no branch is taken and the microprogram
counter register furnishes the next address. When the loop is
ended, either by a count becoming zero, or by passing the
conditional test, the stack is POP’d by decrementing the stack
pointer, since interest in the value contained at the top of the
stack is then complete.
The application of instruction 15 can enhance
performance of a variety of machine-level instructions. For
instance: (1) a memory search instruction to be terminated
either by finding a desired memory content or by reaching the
search limit; (2) variable-field-length arithmetic terminated
early upon finding that the content of the portion of the field still
unprocessed is all zeroes; (3) key search in a disc controller
processing variable length records; (4) normalization of a
floating point number.
Figure 15: 12 LD CNTR & CONTINUE (LDCT)
Instruction 13: Test End-of-Loop.
This instruction provides the capability of conditionally
exiting a loop at the bottom; that is, this is a conditional
instruction that will cause the microprogram to loop via the file
if the test is failed, else to continue to the next sequential
instruction.
Figure 16: 13 TEST END LOOP (LOOP)
Figure 17: 14 CONTINUE (CONT)
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