AD6654CBCZ datasheet(64/88 Pages) AD

Nome de Peças	AD6654CBCZ

Descrição Electrónicos	14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver

PDF	88 Pages

Scroll/Zoom	100%

Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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64 / 88 page

AD6654

Rev. 0 | Page 64 of 88

MSBFIRST

SCLK

SDO

MODE

SCS

SMODE

SDI

BLOCK START ADDRESS

BLOCK COUNT (Nx)

READ

Figure 68. SPI Read MSBFIRST = 0

SPORT MODE TIMING

In SPORT mode, the SCLK continuously runs, and the external

SRFS and STFS signals are used to frame the data. Incoming

framing signals SRFS (receive) and STFS (transmit) are sampled

on the falling edges of SCLK. All input and output data must be

transmitted or received in 8-bit segments starting with the

rising edge after SRFS or STFS is sampled.

SPORT Write

Serial data is sampled on the rising edge of SCLK. The data

should be MSB or LSB first, depending on the polarity of the

MSBFIRST pin. The serial port begins to sample data on the

rising edge of SCLK after SRFS is detected on the falling edge of

SCLK. Once all 8-bits of one byte are shifted in, the data is

transferred to the internal bus.

MSBFIRST

SCLK

SDI

STFS

SDO

MODE

SCS

SMODE

SRFS

BLOCK START ADDRESS

BLOCK COUNT (Nx)

WRITE

N6N5

N4N3

N2N1

D7D6

D5D4

D3D2

D1D0

Figure 69. SPORT Write MSBFIRST = 1

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