AD6654CBCZ datasheet(43/88 Pages) AD

43 / 88 page

AD6654

Rev. 0 | Page 43 of 88

DECIMATING RAM COEFFICIENT FILTER (DRCF)

Following the MRCF is the programmable DRCF FIR filter.

This filter can calculate up to 64 asymmetrical filter taps or up

to 128 symmetrical filter taps. The filter is also capable of a

programmable decimation rate from 1 to 16. A flexible

coefficient offset feature allows loading multiple filters into the

coefficient RAM and changing the filters on the fly. The

decimation phase feature allows a polyphase implementation,

where multiple AD6654 channels are used for processing a

single carrier.

The DRCF filter has 20-bit input and output data and 14-bit

coefficient data. The number of filter taps to calculate is

programmable and is set in the DRCF taps register. The value

of the number of taps minus one is written to this register.

For example, a value of 19 in the register corresponds to

20 filter taps.

The decimation rate is programmable using the 4-bit DRCF

decimation rate word in the DRCF control register. Again, the

value written is the decimation rate minus one.

BYPASS

The DRCF filter can be used in normal operation or bypassed

using the DRCF bypass bit in the DRCF control register. When

the DRCF filter is bypassed, no scaling is applied and the output

of the filter is the same as the input to the DRCF filter.

SCALING

The output of the DRCF filter can be scaled using the 2-bit

DRCF scaling word in the DRCF control register. Table 21 lists

the valid values for the 2-bit word and their corresponding

settings.

Table 21. DRCF Scaling Factor Settings

DRCF Scale Word[1:0]

Scaling Factor

18.06 dB attenuation

12.04 dB attenuation

6.02 dB attenuation

No scaling, 0 dB

SYMMETRY

The DRCF filter does not require symmetrical filters. However,

if the filter is symmetrical, then the symmetry bit in the DRCF

control register should be set. When this bit is set, only half of

the impulse response needs to be programmed into the DRCF

coefficient memory registers. For example, if the number of

filter taps is equal to 15 or 16 and the filter is symmetrical, then

only eight coefficients need to be written into the coefficient

memory. Because a total of 64 taps can be written into the

memory registers, the DRCF can perform 64 asymmetrical

filter taps or 128 symmetrical filter taps.

COEFFICIENT OFFSET

More than one set of filter coefficients can be loaded into

coefficient RAM at any given time (given sufficient RAM

space). The coefficient offset can be used in this case to access

the two or more different filters. By changing the coefficient

offset, the filter coefficients being accessed can be changed on

the fly. This decimal offset value is programmed in the DRCF

coefficient offset register. When this value is changed during the

calculation of a particular output data sample, the sample

calculation is completed using the old coefficients, and the new

coefficient offset from the next data sample calculation is used.

DECIMATION PHASE

When more than one channel of AD6654 is used to process one

carrier, polyphase implementation of corresponding channels’

DRCF or CRCF is possible using the decimation phase feature.

This feature can be used only under certain conditions. The

decimation phase is programmed using the 4-bit DRCF

decimation phase word of the DRCF control register.

MAXIMUM NUMBER OF TAPS CALCULATED

The output rate of the DRCF filter is given by

DRCF

MRCF

DRCF

where:

fMRCF

is the data rate out of the MRCF filter and into the DRCF

filter.

MDRCF

is the decimation rate in the DRCF filter.

The DRCF filter consists of two multipliers (one each for the

I and Q paths). Each multiplier, working at the high speed clock

rate (PLL clock), can do one multiply (or one tap) per high

speed clock cycle. Therefore, the maximum number of filter

taps that can be calculated (symmetrical or asymmetrical filter)

is given by

Maximum Number of Taps

= ceil

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

DRCF

PLLCLK

− 1

where:

fPLLCLK

is the high speed internal processing clock generated by

the PLL clock multiplier.

fDRCF

is the output rate of the DRCF filter, previously calculated.

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