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AD6654BBCZ Folha de dados(PDF) 19 Page - Analog Devices |
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AD6654BBCZ Folha de dados(HTML) 19 Page - Analog Devices |
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19 / 88 page  AD6654 Rev. 0 | Page 19 of 88 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 12 34 5 6 78 9 10 11 12 13 14 15 16 A DGND D14 D12 CPUCLK (SCLK) PC3 PCCH1 PA12 PAIQ PAGAIN PB6 CLK OVR AVDD AVDD AGND AGND A B D7 CHIPID3 CHIPID2 DS (RD, SRFS) PC5 PA5 PA15 PAACK PB2 PB4 EXPC2 DNC AVDD AVDD AGND AGND B C CHIPID0 MODE DTACK (RDY, SDO) R/W (WR, STFS) PC0 PA3 PA9 PACH2 PB9 EXPC1 AVDD AVDD AVDD AGND AGND C D EXT_ FILTER MSB_ FIRST CS (SCS) PC6 PC2 PA1 PA7 PACH0 PB15 EXPC0 DRVDD AVDD AVDD AGND AGND D E CHIPID1 IRP VDDIO VDD CORE PCACK VDD CORE VDD CORE VDD CORE VDDIO VDDIO DRVDD AVDD AVDD AGND AGND E F SMODE D13 D15 RESET D1 VDD CORE VDD CORE VDD CORE VDDIO VDDIO DRVDD AVDD AVDD AGND C2 F G DGND D8 D9 D2 D5 DGND DGND DGND DGND DGND DGND DRVDD AVDD AVDD AGND AGND G H D3 D11 D4 D10 A6 DGND DGND DGND DGND DGND DGND DRVDD AVDD AVDD AGND C1 H J DGND D6 D0 A7 A1 DGND DGND DGND DGND DGND DGND DRVDD AVDD AVDD AGND AGND J K A5 A0 (SDI) A2 PC8 DGND DGND DGND DGND DGND DGND DRVDD AVDD AVDD AGND AGND K L A3 PC11 PC15 PC10 VDDIO VDDIO VDDIO VDD CORE VDD CORE VDD CORE DRVDD AVDD AVDD AGND AIN – L M PC14 PC13 PC9 PC7 PCCH0 VDDIO VDDIO VDDIO VDD CORE VDD CORE VDD CORE DRVDD AVDD AVDD AGND AIN+ M N PC1 PC4 PA13 PA8 PA0 PAREQ PB1 PBREQ DGND DGND DGND DRVDD AVDD AVDD AGND AGND N P PCIQ PCREQ PA14 PA10 PB10 PB7 PB8 PBCH1 PBACK PBCH0 SYNC2 DRVDD AVDD AVDD AGND AGND P R PCCH2 PCGAIN PA6 PA2 PACH1 PB13 PB11 PBCH2 PB14 PBGAIN SYNC1 DRVDD AGND AGND AGND ENC – R T DGND PA11 PA4 PCLK PB5 PB12 PBIQ DGND DNC SYNC0 SYNC3 DR AGND VREF AGND ENC+ T 12 34 5 6 78 9 10 11 12 13 14 15 16 A4 PC12 PB3 PB0 VDDIO VDDIO DNC = DO NOT CONNECT Figure 18. 256 BGA Configuration (Top View) Table 11. Pin Function Descriptions Name Type Pin Number Function POWER SUPPLY AVDD Power See Table 12 5 V Analog ADC Core Supply. DRVDD Power See Table 12 3.3 V ADC Output Driver Supply. VDDCORE Power See Table 12 1.8 V Digital DDC Core Supply. VDDIO Power See Table 12 3.3 V Digital DDC I/O Supply. DGND Ground See Table 12 Digital Core and I/O Ground. AGND Ground See Table 12 Analog ADC Ground. ADC INPUTS AIN+ Input M16 Differential Analog Input. AIN− Input L16 Differential Analog Input. ENC+ Input T16 Differential Encode Input. Conversion initiated on rising edge. ENC− Input R16 Differential Encode Input. ADC OUTPUTS DR Output T12 Data Ready. Inverted and delayed representation of ENC+ used for driving the DDC CLK input. OVR Output A12 Overange Bit. A logic high indicates analog input exceeds ±FS. VREF Output T14 2.4 V Fixed Internal Voltage Reference. Bypass to AGND with 0.1 µF chip capacitor. C1 Output H16 Compensation Pin for ADC Voltage Reference. Bypass to AGND with 0.1 µF chip capacitor. C2 Output F16 Compensation Pin for ADC Voltage Reference. Bypass to AGND with 0.1 µF chip capacitor. |
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