AD6654BBCZ datasheet(62/88 Pages) AD

Nome de Peças	AD6654BBCZ

Descrição Electrónicos	14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver

PDF	88 Pages

Scroll/Zoom	100%

Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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62 / 88 page

AD6654

Rev. 0 | Page 62 of 88

MSBFIRST

SCS

MODE

SDI

SDO

0xaa

0x83

BLOCK START

ADDRESS

RD + COUNT (3)

aa + 1

DATA FROM BLOCK START

ADDRESS

DATA FROM BLOCK START

ADDRESS + 1

DATA FROM BLOCK START

ADDRESS + 2

aa + 2

Figure 64. Serial Read of Three Bytes with MSBFIRST = 0 (All Words are Written or Read LSB First)

SPI MODE TIMING

In SPI mode, the SCLK should run only when data is being

transferred and SCS is logic low. If SCLK runs when SCS is logic

high, the internal shift register continues to run and instruction

words or data are lost. No external framing is necessary. The

SCS pin can be pulled low once for each byte of transfer, or kept

low for the whole length of the transfer.

SPI Write

Data on the SDI pin is registered on the rising edge of SCLK.

During a write, the serial port accumulates eight input bits

of data before transferring one byte to the internal registers.

Figure 65 and Figure 66 show one byte block transfer for

writing in MSBFIRST and LSBFIRST modes.

MSBFIRST

SCLK

SDI

SDO

MODE

SCS

SMODE

BLOCK END ADDRESS

BLOCK COUNT (Nx)

WRITE

N6N5

N4N3

N2N1

D7D6

D5D4

D3D2

D1D0

Figure 65. SPI Write MSBFIRST = 1

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