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HC705JB2GRS/H Folha de dados(PDF) 104 Page - NXP Semiconductors

Nome de Peças HC705JB2GRS/H
Descrição Electrónicos  Industry standard M68HC05 CPU core
PDF  128 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
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HC705JB2GRS/H Folha de dados(HTML) 104 Page - NXP Semiconductors

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GENERAL RELEASE SPECIFICATION
August 28, 1998
EPROM
MC68HC705JB2
11-4
REV 1.1
11.4
MASK OPTION REGISTER (MOR), $01FF
The Mask Option Register (MOR) contains programmable EPROM bits to control
mask options. In order to program this register the MORON bit in PCR need to be
set to “1” before doing the EPROM programming process.
IRQTRIG – IRQ, PA0-PA3 Interrupt Options
1 =
Edge-trigger only
0 =
Edge-and-level-triggered
PULLREN – Port A and B Pullup/Pulldown Options
1 =
Connected
0 =
Disconnected
PAINTEN – PA0-PA3 External Interrupt Options
1 =
Disabled
0 =
Enabled
OSCDLY – Oscillator Delay Option
1 =
128 internal clock cycles
0 =
4064 internal clock cycles
LVREN – LVR Option
1 =
Enabled
0 =
Disabled
bit-7
bit-6
bit-5
bit4
bit-3
bit-2
bit1
bit-0
MOR
$01FF
Read
IRQTRIG
PULLREN
PAINTEN
OSCDLY
LVREN
Write
Erased
0001
1
111
Reset
Unaffected
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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