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HC705JB2GRS/H Folha de dados(PDF) 30 Page - NXP Semiconductors

Nome de Peças HC705JB2GRS/H
Descrição Electrónicos  Industry standard M68HC05 CPU core
PDF  128 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705JB2GRS/H Folha de dados(HTML) 30 Page - NXP Semiconductors

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GENERAL RELEASE SPECIFICATION
August 28, 1998
CENTRAL PROCESSING UNIT
MC68HC705JB2
3-4
REV 1.1
The negative bit is set when the result of the last arithmetic operation, logical
operation, or data manipulation was negative. (Bit 7 of the result was a logical
one.)
The negative bit can also be used to check an often tested flag by assigning the
flag to bit 7 of a register or memory location. Loading the accumulator with the
contents of that register or location then sets or clears the negative bit according
to the state of the flag.
3.6.4 Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logical
operation, data manipulation, or data load operation was zero.
3.6.5 Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred
during the last arithmetic operation, logical operation, or data manipulation. The
carry/borrow bit is also set or cleared during bit test and branch instructions and
during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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