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HC705JB2GRS/H Folha de dados(PDF) 50 Page - NXP Semiconductors

Nome de Peças HC705JB2GRS/H
Descrição Electrónicos  Industry standard M68HC05 CPU core
PDF  128 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
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HC705JB2GRS/H Folha de dados(HTML) 50 Page - NXP Semiconductors

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GENERAL RELEASE SPECIFICATION
August 28, 1998
INPUT/OUTPUT PORTS
MC68HC705JB2
7-4
REV 1.1
7.2
PORT B
Port B is a 3-bit bidirectional port which functions as shown in Figure 7-2. Each
Port B pin is controlled by the corresponding bits in a data direction register, a
data register, and a pulldown/up register. The Port B Data Register is located at
address $0001. The Port B Data Direction Register (DDRB) is located at address
$0005. The Port B Pulldown/up Register (PDURB) is located at address $0011.
Reset clears the DDRB and the PDURB. The Port B Data Register is unaffected
by reset.
PB0 is a standard push-pull I/O pin with pulldown option; and is shared with TCAP.
PB1 and PB2 are of open-drain type, with pullup option, each capable of sinking
25mA (typical) current at VOL 0.5V max. These two pins may be connected
together to constitute a single pin capable of sinking 50mA (typical). In this case,
both PB1 and PB2 data bits will have to be written with the same value at the
same write cycle.
Figure 7-2. Port B I/O Circuitry
7.2.1 Port B Data Register
All Port B I/O pins have a corresponding bit in the Port B Data Register. When a
Port B pin is programmed as an output the state of the corresponding data
register bit determines the state of the output pin. When a Port B pin is
programmed as an input, any read of the Port B Data Register will return the logic
state of the corresponding I/O pin. The Port B data register is unaffected by reset.
Unused bits will always read as logic zeros, and any write to these bits will be
ignored. The Port B data register is unaffected by reset.
Write $0011
Read $0001
Write $0001
Read $0005
Write $0005
Internal HC05
Data Bus
100
µA
Pulldown
Data
Register Bit
Output
Mask Option
(Software Pulldown/up Inhibit)
Reset
(RST)
Data Direction
Register Bit
Pulldown/up
Register Bit
VDD
100K
Pullup
Note: Each I/O port pin can have either pullup or pulldown device, but not both.
PB1 and PB2 output drivers are of open-drain type
I/O Pin
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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