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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

Parameter

Description

VCCIO=1.8V

VCCIO=2.5V

VCCIO=3.3V

Units

Min

Max

Min

Max

Min

Max

Tsclk

SPI clock period

(SINGLE/DUAL

mode)

33.3

Tsclk

SPI clock period

(QUAD mode)

Tsclkl

SPI clock low

duration

Tsclkh

SPI clock high

duration

Tsac

SPI access time

3.5

Tisu

Input Setup

3.5

Tih

Input Hold

Tzo

Output enable delay

Toz

Output disable delay

Tod

Output data delay

Tcsnh

CSN hold time

Table 6-9 SPI Interface Timing Specification

6.4.3

RGB Interface Timing

Parameter

Description

Value

Units

Min

Typ

Max

Tpclk

Pixel Clock period

15.7

Tpclkdc

Pixel Clock duty cycle

Output delay relative to PCLK rising

edge (REG_PCLK_POL=0) or falling

edge (REG_PCLK_POL=1). Applied for

all the RGB output pins.

Output hold time relative to PCLK

rising edge (REG_PCLK_POL=0) or

falling edge (REG_PCLK_POL=1).

Applied for all the RGB output pins.

0.5

Table 6-10 RGB interface timing characteristics

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