FT812Q-R datasheet(19/63 Pages) BRIDGETEK

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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

1st Byte

2nd byte

3rd byte

Command

Description

02h

GPIO 2

03h

GPIO 3

04-07h

Reserved

08h

DISP

09h

0Ah

VSYNC / HSYNC

0Bh

PCLK

0Ch

BACKLIGHT

0Dh

R[7:0], G[7:0], B[7:0]

0Eh

AUDIO_L

0Fh

INT_N

10h

CTP_RST_N

11h

CTP_SCL

12h

CTP_SDA

13h

SPI MISO/MOSI/IO2/IO3

Others

Reserved

Note: GPIO0 shares the same pin as SPI

IO2 and GPIO1 with SPI IO3. When SPI is

set in Quad mode, IO2 and IO3 will inherit

the drive strength set in GROUP 13h;

otherwise GPIO0 and GPIO1 will inherit the

drive strength from GROUP 00h and 01h

respectively.

01110001b

00000000b

71h

PIN_PD_STA

During power down, all output and in/out

pins will not be driven.

Please refer to

Error! Reference source not found. for

their default power down state.

These settings will only be effective during

power down and will not affect normal

operations.

Also

note

that

these

configuration bits are sticky and, unlike

other configuration bits, will not reset to

default values upon exiting power down.

Only POR will reset them.

Byte2 determines which pin and the setting

are to be updated.

Byte2[1:0] determine the pin state.

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