ST7293 datasheet(5/69 Pages) STMICROELECTRONICS

5 / 69 page

5/69

ST7294

1.2 PIN DESCRIPTION

VDD Power supply.

VSS Ground.

OSCin, OSCout

Oscillator input and output

pins. These pins are usually connected to a paral-

lel resonant crystal or ceramic resonator. An ex-

ternal clock source may also be input via OSCin.

RESET

An active-low input signal on this pin

forces initialisation of the MCU. This is the highest

priority interrupt and it is not maskable. This pin is

set to an output-low level following release on the

part of the Watchdog. The pin may be used to re-

set external peripherals.

INT This is the external interrupt input, which may

be software-configured in one of four triggering

modes.

Caution:

The INT pin is also used to select an in-

ternal non-user test mode reserved exclusively for

use by SGS-THOMSON Microelectronics. This

non-user mode is entered on the rising edge of the

Reset signal, if:

– the voltage applied to the INT pin is less than

VDD + 0.5V, the device will initialise correctly in

User mode;

– if a “high” voltage (typically > VDD +3V, @ VDD

= +5V) is applied to the pin, the device will start

in a reserved non-user mode.

Under certain operating conditions apparent de-

vice malfunction may be experienced: this may be

described as follows:

During the Reset phase, if the VDD supply risetime

is slow, the Reset rising edge may occur at a volt-

age level lower than the minimum allowed voltage

of 2.5V. In this case, the “high” voltage which

needs to be applied to the INT pin to enter the spe-

cial mode may be as low as 3.5V, and such a volt-

age level may be supplied by the external interrupt

source, thus provoking an apparent system mal-

function.

For this reason it is strongly recommended to

manage the INT pin, either by tying it to VDD, if

unused, or by connecting it to VDD via a diode, if it

is to be used: this will avoid unexpected entry into

non-user mode.

ICAP (PC0). Input Capture signal directed to the

TIMER system. This pin, according to the chosen

mask option, may be defined as the ICAP function

input, or as a standard PC0 pin. When the pin is

defined as the ICAP input, the internal pull-up re-

sistor is not connected.

OCMP1 (PC1). Output Compare signal originating

from the TIMER system. This pin may, depending

on the chosen mask option, be defined as the

OCMP1 function output (Output Compare 1 of the

Timer) or as a standard PC1 pin. When the pin is

defined as OCMP1, the internal pull-up resistor is

not connected.

PA0-PA7, PB0-PB7, PC0-PC5. These 22 lines

are standard I/O lines, programmable as either in-

puts or outputs.

– PORT A

8 standard I/O lines, bit-programma-

ble via the DDRA and DRA registers. Depending

on the chosen mask option, the outputs may be

defined as standard push-pull or as open-drain.

A further mask option allows a resistor to be add-

ed on each line when it is defined as an input.

– PORT B

8 standard I/O lines bit-programmable

via the DDRB and DRB registers. A mask option

allows a resistor to be added on each line when

it is defined as an input.

– PORT C

6 standard I/O lines bit-programma-

ble via the DDRC and DRC registers. Depending

on the chosen mask option, these 6 lines can be

defined as 6 falling-edge-sensitive interrupt lines,

linked to a single interrupt vector, or as 6 stand-

ard input ports tied to V

DD through an internal pull-

up resistor. These negative edge sensitive inter-

rupt lines are capable of waking-up the ST7294

from WAIT or HALT mode. This feature allows

one to build low power applications where the

ST7294 can be woken-up by a key being

pressed.

ST7293 Folha de dados(PDF) 5 Page - STMicroelectronics

ST7293 Folha de dados(HTML) 5 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Folha de dados Download

Ligação URL