SPC58EG80C3 datasheet(105/139 Pages) STMICROELECTRONICS

105 / 139 page

DS11758 Rev 6

105/139

SPC584Gx, SPC58EGx, SPC58NGx

Electrical characteristics

106

4.17.7

I2C timing

The I2C AC timing specifications are provided in the following tables.

Note:

In the following table, I2C input timing is valid for Automotive and TTL inputs levels,

hysteresis enabled, and an input edge rate no slower than 1 ns (10% – 90%).

Note:

In the following table:

•

All output timing is worst case and includes the mismatching of rise and fall times of the

output pads.

Table 61. UART frequency support

LINFlexD clock

frequency LIN_CLK

(MHz)

Oversampling rate

Voting scheme

Max usable frequency

(Mbaud)

3:1 majority voting

810

Limited voting on one

sample with configurable

sampling point

13.33

516

420

100

3:1 majority voting

6.25

12.5

Limited voting on one

sample with configurable

sampling point

16.67

520

425

Table 62. I2C input timing specifications – SCL and SDA

No. Symbol C

Parameter

Value

Unit

Min

Max

— CC D Start condition hold time

—

PER_CLK

Cycle(1)

— CC D Clock low time

—

PER_CLK Cycle

— CC D Bus free time between Start and Stop condition

4.7

—

µs

— CC D Data hold time

0.0

—

— CC D Clock high time

—

PER_CLK Cycle

— CC D Data setup time

0.0

—

— CC D Start condition setup time (for repeated start condition only)

—

PER_CLK Cycle

— CC D Stop condition setup time

—

PER_CLK Cycle

1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the

device reference manual for more detail.

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