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KTZ8866

January 2022 - Revision 04b

Page 25 of 37

Company Confidential

There are two kinds of I2C data transfer cycles: write cycle and read cycle.

I2C Write Cycle

For I2C write cycle, data is transferred from a master to a slave. The first byte transmitted is the 7-bit slave

address plus one bit of ‘0’ for write. Next follows a number of data bytes. The slave returns an acknowledge bit

after each received byte. Data is transferred with the most significant bit (MSB) first. Figure 6 shows the

sequence of the I2C write cycle.

Figure 6. I2C Write Cycle

I2C Write Cycle Steps:

• Master generates start condition.

• Master sends 7-bit slave address (0010001 for KTZ8866) and 1-bit data direction ‘0’ for write.

• Slave sends acknowledge if the slave address is matched.

• Master sends 8-bit register address.

• Slave sends acknowledge.

• Master sends 8-bit data for that addressed register.

• Slave sends acknowledge.

• If master sends more data bytes, the register address will be incremented by one after each acknowledge.

• Master generate stop condition to finish the write cycle.

I2C Read Cycle

For I2C read cycle, data is transferred from a slave to a master. But to start the read cycle, master needs to write

the register address first to define which register data to read. Figure 7 shows the steps of the I2C read cycle.

Figure 7. I2C Read Cycle

I2C Read Cycle Steps:

• Master generates start condition.

• Master sends 7-bit slave address (0010001 for KTZ8866) and 1-bit data direction ‘0’ for write.

• Slave sends acknowledge if the slave address is matched.

• Master sends 8-bit register address.

• Slave sends acknowledge.

• Master generates repeated start condition.

• Master sends 7-bit slave address (0010001 for KTZ8866) and 1-bit data direction ‘1’ for read.

• Slave sends acknowledge if the slave address is matched.

• Slave sends the data byte of that addressed register.

• If master sends acknowledge, the register address will be incremented by one after each acknowledge and

the slave will continue to send the data for the updated addressed register.

• If master sends no acknowledge, the slave will stop sending the data.

• Master generate stop condition to finish the read cycle.

From Slave to Master

S

Device Address

Register Address

0

A

A

Data

A

P

From Master to Slave

‘0’

Write

7 bits

8 bits

8 bits

S = Start

A = Acknowledge (SDA Low)

P = Stop

Rs

Device Address

1

A

P

‘1’

Read

7 bits

8 bits

S

Device Address

Register Address

0

A

A

‘0’

Write

7 bits

8 bits

Data

A*

From Slave to Master

From Master to Slave

S = Start

Rs = Repeated Start

A = Acknowledge (SDA Low)

A* = No Acknowledge (SDA High)

P = Stop