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XIO2000 Folha de dados(PDF) 82 Page - Texas Instruments

Nome de Peças XIO2000
Descrição Electrónicos  XIO2000 PCI Express to PCI Bus Translation Bridge
PDF  150 Pages
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Fabricante Electrônico  TI [Texas Instruments]
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XIO2000 Folha de dados(HTML) 82 Page - Texas Instruments

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Classic PCI Configuration Space
70
November 2005
SCPS097B
4.59 GPIO Control Register
This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of
GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO0
(CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). See Table 4−33 for a complete
description of the register contents.
PCI register offset:
B4h
Register type:
Read-only, Read/Write
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−33. GPIO Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:8
RSVD
R
Reserved. Returns 00h when read.
7†
GPIO7_DIR
RW
GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.
0 = Input (default)
1 = Output
6†
GPIO6_DIR
RW
GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.
0 = Input (default)
1 = Output
5†
GPIO5_DIR
RW
GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.
0 = Input (default)
1 = Output
4†
GPIO4_DIR
RW
GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.
0 = Input (default)
1 = Output
3†
GPIO3_DIR
RW
GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.
0 = Input (default)
1 = Output
2†
GPIO2_DIR
RW
GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.
0 = Input (default)
1 = Output
1†
GPIO1_DIR
RW
GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.
0 = Input (default)
1 = Output
0†
GPIO0_DIR
RW
GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.
0 = Input (default)
1 = Output
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.



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