XIO2000 datasheet(48/150 Pages) TI

48 / 150 page

Feature/Protocol Descriptions

November 2005

SCPS097B

Table 3−13. EEPROM Register Loading Map

SERIAL EEPROM

WORD ADDRESS

BYTE DESCRIPTION

00h

PCI-Express to PCI bridge function indicator (00h)

01h

Number of bytes to download (1Eh)

02h

PCI 84h, subsystem vendor ID, byte 0

03h

PCI 85h, subsystem vendor ID, byte 1

04h

PCI 86h, subsystem ID, byte 0

05h

PCI 87h, subsystem ID, byte 1

06h

PCI D4h, general control, byte 0

07h

PCI D5h, general control, byte 1

08h

PCI D6h, general control, byte 2

09h

PCI D7h, general control, byte 3

0Ah

PCI D8h, clock control

0Bh

PCI D9h, clock mask

0Ch

Reserved—no bits loaded

0Dh

PCI DCh, arbiter control

0Eh

PCI DDh, arbiter request mask

0Fh

PCI C0h, control and diagnostic register 0 byte 0

10h

PCI C1h, control and diagnostic register 0 byte 1

11h

PCI C2h, control and diagnostic register 0 byte 2

12h

PCI C3h, control and diagnostic register 0 byte 3

13h

PCI C4h, control and diagnostic register 1 byte 0

14h

PCI C5h, control and diagnostic register 1 byte 1

15h

PCI C6h, control and diagnostic register 1 byte 2

16h

PCI C7h, control and diagnostic register 1 byte 3

17h

PCI C8h, control and diagnostic register 2 byte 0

18h

PCI C9h, control and diagnostic register 2 byte 1

19h

PCI CAh, control and diagnostic register 2 byte 2

1Ah

PCI CBh, control and diagnostic register 2 byte 3

1Bh

Reserved—no bits loaded

1Ch

Reserved—no bits loaded

1Dh

PCI E0h, serial IRQ mode control

1Eh

PCI E2h, serial IRQ edge control, byte 0

1Fh

PCI E3h, serial IRQ edge control, byte 1

20h

End-of-list indicator (80h)

This format must be explicitly followed for the bridge to correctly load initialization values from a serial

EEPROM. All byte locations must be considered when programming the EEPROM.

The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is internally

hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the

EEPROM are tied to VSS to achieve this address. The serial EEPROM in the sample application circuit

(Figure 3−14) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to

the chip, and the sample application shows these terminal inputs tied to VSS.

During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is

asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may

be monitored to verify a successful download.

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