M2050/51/52 Datasheet Rev 1.0

7 of 12

Revised 23Jun2005

Integ r ated Circuit Systems, Inc. ● Communications Modules ● www.ics t.com ● tel (508) 852-5400

M2050/51/52

Preliminar y In f o r m atio n

Integrated

Circuit

Systems, Inc.

Optional Hitless Switching and Phase Build-out

The M2050/51/52 is available with a Hitless Switching

feature that is enabled during device manufacturing.

In addition, a Phase Build-out feature is also offered.

These features are offered as device options and are

specified by device order code. Refer to “Ordering

Information” on pg. 12.

The Hitless Switching feature (with or without Phase

Build-out) is designed for applications where switching

occurs between two stable system reference clocks. It

should not be used in loop timing applications, or when

reference clock jitter is greater than 1 ns pk-pk. The

Hitless Switching sequence is triggered by the LOL

circuit, which is activated by a 4 ns phase transient.

This magnitude of phase transient can generated by the

CDR (Clock & Data Recovery unit) in loop timing mode,

especially during a system jitter tolerance test. It can

also be generated by some types of Stratum clock

DPLLs (digital PLL), especially those that do not include

a post de-jitter APLL (analog PLL).

When the M2050/51/52 is operating in wide bandwidth

puts the device into narrow bandwidth mode when

activated. This allows the PLL to lock the new input

clock phase gradually. With proper configuration of the

external loop filter, the output clock phase change

complies with MTIE and TDEV specifications for

GR-253 (SONET) and ITU G.813 (SDH) during input

reference clock changes.

The optional proprietary Phase Build-out (PBO)

function enables the PLL to absorb most of the phase

change of the input clock during reference switching.

The PBO function selects a new VCSO clock edge for

the PLL Phase Detector feedback clock, selecting the

edge closest in phase to the new input clock phase.

This reduces re-lock time, the generation of wander,

and extra output clock cycles.

The Hitless Switching and Phase Build-out functions

a low phase detector frequency must be avoided. See

“Guidelines for Using LOL” on pg. 6 for information

regarding the phase detector frequency.

HS/PBO Sequence Trigger Mechanism

The HS function (or the combined HS/PBO function)

is armed after the device locks to the input clock

reference. Once armed, HS is triggered by the

occurance of a Loss of Lock condition. This would

typically occur as a consequence of a clock reference

failure, a clock failure upstream to the M2050/51/52, or

a M2050/51/52 clock reference mux reselection.

HS/PBO Operation

Once triggered, the following HS/PBO sequence

occurs:

1. The HS function disables the PLL Phase Detector

and puts the device into NBW (narrow bandwidth)

mode. The internal resistor Rin is changed to

2100k

Ω . See the Narrow Bandwidth (NBW) Control

Pin on pg. 6.

2. If included, the PBO function adds to (builds out) the

phase in the clock feedback path (in VCSO clock

cycle increments) to align the feedback clock with

the (new) reference clock input phase.

3. The PLL Phase Detector is enabled, allowing the

PLL to re-lock.

4. Once the PLL Phase Detector feedback and input

clocks are locked to within 2 nsec for 8 consecutive

cycles, a timer (WBW timer) for resuming wide

bandwidth (in 175 nsec) is started.

5. When the WBW timer times out, the device reverts

to wide loop bandwidth mode (i.e., Rin is returned to

100k

Ω) and the HS/PBO function is re-armed.

basis and may be intermittent until PLL phase lock has

fully stabilized.