M2050/51/52 Datasheet Rev 1.0

4 of 12

Revised 23Jun2005

Integrate d Circu it Systems, Inc. ● Communications Modules ● www.ics t.com ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M2050/51/52

Preliminar y In f o r m atio n

Use this option to demap from either “10GbE LAN” or

“10GbE 255/238 FEC” encoded to “10GbE”. Also use

this option to operate in 10GbE repeater mode.

The de-mapper FEC PLL ratios (in Table 5) enables

the M2051-11-625.0000 to accept “base” input

reference frequencies of:

625.00

644.5313

669.6429

The Mfec divider value for the first three settings allows

one set of passive filter components to be used for all

three of these modes.

The fourth setting maps “10GbE 255/238 FEC” using

the lowest Mfec value possible. Use this setting to

produce the maximum loop bandwidth.

This option de-maps from both “10GbE LAN 255/237

FEC” and “10GbE LAN 255/238 FEC” to “10GbE LAN”.

Also use this option to operate in 10GbE LAN repeater

mode.

The de-mapper FEC PLL ratios (in Table 6) enables

the M2052-11-625.0000 to accept “base” input

reference frequencies of:

644.5313

690.5692

693.4830

Use this option for multi-rate de-mapping applications

that require one set of PLL passive filter values to

operate over both “10GbE LAN 255/237 FEC” and

“10GbE LAN 255/238 FEC”. The Mfec divider value is

kept nearly constant to maintain similar loop bandwidth

using one set of external filter component values.

P Divider Look-Up Table (LUT)

also available, plus a TriState mode. The outputs can

be placed into the valid state combinations as listed in

Table 7. (The outputs cannot each be placed into any of

the five available states independently.)

General Guideline for Mfec and Rfec Divider Selection

overly sensitive, and higher phase detector frequencies

during loop timing mode.

The M2050/51/52 is a PLL (Phase Locked Loop) based

clock generator that generates output clocks synchro-

nized to one of two selectable input reference clocks.

An internal high "Q" SAW delay line provides low jitter

signal performance and establishes the output

frequency of the VCSO (Voltage Controlled SAW

Oscillator). In a given M2050/51/52 device, the VCSO

center frequency is fixed. A common center frequency

applications. The VCSO center frequency is specified at

time of order (see “Ordering Information” on pg. 12).

The VCSO has a guaranteed tuning range of ±120 ppm

(commercial temperature grade).

Pin selectable dividers are used within the PLL and

for the output clock. This enables tailoring of device

functionality and performance. The FEC feedback and

reference dividers (the “Mfec Divider” and “Rfec

Divider”) provide the multiplication ratios necessary to

accomodate clock translation for both forward and

inverse Forward Error Correction. The Mfec and Rfec

FEC_SEL1:0

1

0

Description

Base Input

Rate (MHz)

Fvcso =

Base Output

Rate (MHz)

For M2051 with Fvcso = 625.00

0 0

644.5313 625.0000

0 1

625.0000 625.0000

1 0

1 1

Table 5: M2051: De-map LUT (10GbE LAN or 255/238 FEC to 10GbE)

FEC_SEL1:0

1

0

Description

Base Input

Rate (MHz)

Fvcso =

Base Output

Rate (MHz)

For M2052 with Fvcso = 625.00

0 0

79 85

10GbE LAN

255/237 FEC to

10GbE LAN

693.4830 625.0000

0 1

644.5313 625.0000

1 0

84 90

10GbE LAN

255/238 FEC to

10GbE LAN

690.5692 625.0000

1 1

644.5313 625.0000

Table 6: M2052: De-map LUT (255/237 or 255/238 FEC to 10GbE LAN)

P_SEL2:0

P Value

M2050-625.0000

Output Frequency (MHz)

FOUT0

FOUT1

0 0 0

25

1

25.00 625.00

0 0 1

25

4

25.00 156.25

0 1 0

1

1

625.00 625.00

0 1 1

4

1

156.25 625.00

1 0 0

5

5

125.00 125.00

1 0 1

4

4

156.25 156.25

1 1 0

5

4

125.00 156.25

1 1 1

TriState TriState

N/A

N/A

Table 7: P Divider Look-Up Table (LUT)