PIC10F200T datasheet(15/86 Pages) MICROCHIP

15 / 86 page

Preliminary

DS41239B-page 13

PIC10F200/202/204/206

3.1

Clocking Scheme/Instruction

Cycle

The clock is internally divided by four to generate four

non-overlapping quadrature clocks, namely Q1, Q2,

Q3 and Q4. Internally, the PC is incremented every Q1

and the instruction is fetched from program memory

and latched into the instruction register in Q4. It is

decoded and executed during the following Q1 through

Q4. The clocks and instruction execution flow is shown

in Figure 3-3 and Example 3-1.

3.2

Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the PC to change (e.g., GOTO), then two cycles

are required to complete the instruction (Example 3-1).

A fetch cycle begins with the PC incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-3:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

OSC1

PC + 1

PC + 2

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

1. MOVLW 03H

Fetch 1

Execute 1

2. MOVWF GPIO

Fetch 2

Execute 2

3. CALL

SUB_1

Fetch 3

Execute 3

4. BSF

GPIO, BIT1

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

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