MSK5045-3.3H datasheet(4/9 Pages) MSK

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The output capacitor values are generally determined

by the ESR and voltage rating requirements rather than

capacitance requirements for stability. Low ESR capaci-

tors that meet the ESR requirement usually have more

output capacitance than required for stability. Only spe-

cialized low-ESR capacitors intended for switching-regu-

lator applications, such as AVX TPS, Sprague 595D,

Sanyo OS-CON, Nichicon PL series or Kemet T510 se-

ries should be used. The capacitor must meet minimum

capacitance and maximum ESR values as given in the

following equations:

CF > 2.5V(1 + VOUT/VIN(MIN))

VOUT x RSENSE x f

RESR < RSENSE x VOUT

2.5V

OUTPUT CAPACITOR SELECTION:

These equations provide 45 degrees of phase margin

to ensure jitter-free fixed-frequency operation and pro-

vide a damped output response for zero to full-load step

changes.

Lower quality capacitors can be used if the

load lacks large step changes. Bench testing over tem-

perature is recommended to verify acceptable noise and

transient response.

As phase margin is reduced, the

first symptom is timing jitter, which shows up in the

switching waveforms. Technically speaking, this typi-

cally harmless jitter is unstable operation, since the

switching frequency is non-constant. As the capacitor

ESR is increased, the jitter becomes worse. Eventually,

the load-transient waveform has enough ringing on it

that the peak noise levels exceed the output voltage tol-

erance. With zero phase margin and instability present,

the output voltage noise never gets much worse than

IPEAK x RESR (under constant loads). Designers of indus-

trial temperature range digital systems can usually multi-

ply the calculated ESR value by a factor of 1.5 without

hurting stability or transient response.

The output ripple is usually dominated by the ESR of

the filter capacitors and can be approximated as IRIPPLE

x RESR. Including the capacitive term, the full equation

for ripple in the continuous mode is VNOISE(p-p)=IRIPPLE

x (RESR + 1/(2

πfC)). In pulse skipping mode, the induc-

tor current becomes discontinuous with high peaks and

widely spaced pulses, so the noise can actually be higher

at light load compared to full load. In pulse skipping mode,

the output ripple can be calculated as follows:

VNOISE(p-p)= 0.02 x RESR + 0.0003 x 6.4µH x [1/VOUT+1/(VIN-VOUT)]

RSENSE

(RSENSE)² x C

APPLICATION NOTES CONT'D

OUTPUT INDUCTOR (OPTIONAL):

Placing an output inductor between the package and

the sense resistor will reduce output ripple and noise.

Output ripple and noise increase as the input to output

voltage differential increases. Ouput ripple is also higher

when the MSK 5045 is operated in power save mode.

Optional inductance will directly add to the internal in-

ductance of the device and should be included in peak to

peak current calculations (see SELECTING RS). Since ad-

ditional inductance will affect the output response of the

regulator, the inductance value must be carefully selected

for each application.

RFB:

Rev. G 2/06

ENABLE FUNCTION:

The MSK 5045 is enabled by applying a logic level high to

the Enable pin or leaving it open. A logic level low will disable

the device and quiescent input current will reduce to approxi-

mately 1mA. The Enable threshold voltage is 1V. If automatic

start up is required, simply make no connection. Maximum En-

able voltage is +10.5V. The Enable pin has an internal pull up

resistor to 10.5V.

CURRENT LIMITING:

Current limiting the MSK5045 is achieved by setting the

cycle-by-cycle current limit as described in the section titled

SELECTING RS. The designer must set the peak current limit

such that the average output current will not exceed the appli-

cation limits. In a short circuit condition the average output cur-

rent will approach the peak current limit. RS should be selected

such that the average output current will not exceed 4.0 Amps.

RS must be small enough to allow for the required load current

plus the peak ripple current; 80mV/RS=IOUT+½Ip-p. Load

components should be sized to withstand a maximum current

of 120mV/RS

It is very important that the DC voltage returned to the

RFB pin from the output be as noise and oscillation free

as possible. This voltage helps to determine the final out-

put and therefore must be a clean voltage. Excessive noise

or oscillation can cause the device to have an incorrect

output voltage. Proper PC board layout techniques can

help to achieve a noise free voltage at the RFB pin.

POWER SAVE MODE:

Power save mode is enabled by applying a logic low to

the PWR SAVE pin and disabled by applying a logic high

or leaving it open. The MSK5045 will skip switching pulses

to save gate drive current in Q1 and Q2 when operated

under light load with power save enabled. MSK5045

senses the voltage across RS and skips most switching

pulses when the voltage falls below 30mV indicating a

light load condition. The oscillator is gated off because

the minimum current comparator resets the high side latch

at the start of each cycle until the voltage feedback sig-

nal falls below the output voltage set point. Under heavy

loads the voltage across RS does not fall below 30mV

and the MSK5045 operates in full PWM mode at 300

KHz.

Disabling the power save mode sets the PWM to

300KHz constant switching frequency for low noise mode

operation. Maximum input voltage on the PWR SAVE pin

is 5.5V. The PWR SAVE pin has an internal pull-up resis-

tor to 5V. RS should not be eliminated when power save

is disabled because it provides cycle-by-cycle current lim-

iting and synchronous rectifier control as described in the

SEQUENCE OF OPERATION paragraph. Refer to table 1

for power save mode operational characteristics.

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