ADIN2111BCPZ-R7 datasheet(65/125 Pages) AD

65 / 125 page

Data Sheet

ADIN2111

REGISTERS

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Rev. 0 | 65 of 125

Table 69. Bit Descriptions for SOFT_RST

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

[15:0]

RST_KEY

Software Reset. Write a pair of keys in order and back to back on the SPI to trigger a reset.

0x0

0x4F1C: Key 1 to reset the MAC logic only.

0xC1F4: Key 2 to reset the MAC logic only. Reset does not take effect until CS is brought high and CS must

be held asserted for at least 100 ns for the reset to take effect. If the MACPHY is in software power-down, the

MAC_ONLY reset has no effect. That is, CRSM_SFT_P_CNTRL.CRSM_SFT_PD must be 0.

0x6F1A: Key 1 to request release of reset to the MAC core logic. Use MAC_RST_EXIT_REQ_KEYx to request

a release of reset to the MAC core logic when the 25 MHz crystal clock is not available. This brings the MAC out

of reset using the oscillator clock (12.5 MHz to 25.7 MHz). SPI accesses can then proceed at 15 MHz to allow

debug access to MAC and PHY registers.

0xA1F6: Key 2 to request release of reset to the MAC core logic.

Inject an Error on MISO from the DUT Register

Address: 0x3D, Reset: 0x00000000, Name: SPI_INJ_ERR

Table 70. Bit Descriptions for SPI_INJ_ERR

Bits

Bit Name

Description

Reset

Access

[31:1]

RESERVED

Reserved.

0x0

TEST_SPI_INJ_ERR

Inject an Error on the SPI MISO Path. This function allows software to test that errors received on

MISO are properly detected in software.

0x0

R/W

If set and using the OPEN Alliance SPI protocol for data transaction, the parity bit in the Rx footer is

inverted. Also, the time stamp parity bit in the in Rx footer is inverted.

If set and using the OPEN Alliance SPI protocol for protected control burst write transactions, starting

from the second word in a burst, the MSB of each echoed 32-bit word is inverted.

If set and using the OPEN Alliance SPI protocol for protected control read transactions, the MSB of

each 32-bit complement word is inverted.

If set and using the generic SPI protocol with protection enabled, the CRC8 returned on a register read

is inverted.

FIFO Sizes Register

Address: 0x3E, Reset: 0x02222222, Name: FIFO_SIZE

Before modifying the FIFO sizes, frame reception and transmission must be stopped and the FIFOs must be empty.

Configure ADDR_RULE to drop all frames and set Px_UNK2HOST and Px_UNK2Px to 0 to ensure all received frames are dropped.

Use LES_FIFO_CLR to reset the FIFOs. Then the FIFO sizes can be modified.

The total FIFO size must be less than or equal to 28 kB.

Table 71. Bit Descriptions for FIFO_SIZE

Bits

Bit Name

Description

Reset

Access

[31:28]

RESERVED

Reserved.

0x0

[27:24]

P2_TX_SIZE

Port 1 to Port 2 Transmit FIFO Size.

0x2

R/W

0000: 0 bytes.

0001: 2 kB.

0010: 4 kB.

0011: 6 kB.

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