ADP5056ACCZ-R7 datasheet(23/31 Pages) AD

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Data Sheet

ADP5056

Rev. 0 | Page 23 of 31

PROGRAMMING THE UVLO INPUT

The precision enable input can program the UVLO threshold of

the input voltage, as shown in Figure 30.

The precision turn on threshold is 0.615 V, and the turn off

threshold is 0.575 V. Use the following equations to calculate the

resistive voltage divider for the programmable VIN turn on

voltage and the VIN turn off voltage:

VIN_RISING = (3.5 μA + 0.615 V/RBOT_EN) × RTOP_EN + 0.615 V

VIN_FALLING = (0.9 μA + 0.575 V/RBOT_EN) × RTOP_EN + 0.575 V

where:

VIN_RISING is the VIN turn on voltage.

VIN_FALLING is the VIN turn off voltage.

RBOT_EN is the resistor from ENx to ground.

RTOP_EN is the resistor from VIN to ENx.

SLOPE COMPENSATION SETTING

The slope compensation is necessary in a current mode control

architecture to prevent subharmonic oscillation and to maintain

a stable output. The ADP5056 uses the emulated current mode,

and the slope compensation is implemented by connecting a

resistor (RRAMPX) from the RAMPx pin to ground.

Theoretically, an extra slope of VOUT/(2 × L) is enough to stabilize

the system. To guarantee that any noise is decimated in one

cycle and the system is stable from subharmonic oscillation, the

ADP5056 uses an extra slope of VOUT/L.

Calculate the ramp resistor values, RRAMPx, in kΩ, by using the

following equations:

RRAMP1= L1 × 500

RRAMP2 = L2 × 500

RRAMP3 = L3 × 226

where L1, L2, and L3 are the inductor values in each channel,

in μH.

COMPENSATION COMPONENTS DESIGN

For current mode control, the power stage can be simplified as a

voltage controlled current source that supplies current to the

output capacitor and load resistor. The simplified loop is

composed of one domain pole and a zero contributed by the

output capacitor ESR. The control-to-output transfer function is

shown in the following equations:

()

OUT

COMP















 











where:

s is the domain in the control to output transfer function.

AVI = 12.5 A/V for Channel 1 and Channel 2, 5 A/V for Channel 3.

R is the load resistance.

fz is the zero frequency.

fp is the pole frequency.

ESR

OUT











ESR

OUT











where COUT is the output capacitance.

The ADP5056 uses a transconductance amplifier as the error

amplifier to compensate the system. Figure 45 shows the

simplified peak current mode control small signal circuit.

RESR

–

CCP

COUT

RTOP

RBOT

–

AVI

VOUT

VCOMP

VOUT

Figure 45. Simplified Peak Current Mode Control Small Signal Circuit

The compensation components, RC and CC, contribute a zero.

RC and the optional CCP contribute an optional pole.

The closed-loop transfer equation is as follows:

()

BOT

TOP

CCP































The following guidelines show how to select the compensation

components—RC, CC, and CCP—for ceramic output capacitor

applications.

Determine the cross frequency (fC). Generally, fC is between

fSW/12 and fSW/6.

Calculate RC using the following equation:

0.6

OUT

mVI











Place the compensation zero at the domain pole (fP).

Calculate CC using the following equation:

()

ESR

OUT





CCP is optional. CCP can be used to cancel the zero caused

by the ESR of the output capacitor. Calculate CCP using the

following equation:

ESR

OUT





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