ADP5056ACCZ-R7 datasheet(20/31 Pages) AD

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ADP5056

Data Sheet

Rev. 0 | Page 20 of 31

UVLO

Undervoltage lockout circuitry monitors both bias input voltage

(VBIAS pin) and power input voltage level (PVINx pin) of each

buck regulator in the ADP5056. If the power input voltage falls

below 2.22 V (typical falling threshold), the corresponding

channel is turned off. After the input voltage rises above 2.5 V

(typical rising threshold), the soft start period initiates, and the

corresponding channel enables when the ENx pin is high.

If the bias voltage falls below 3.8 V (typical falling threshold), all

channels turn off. After the bias voltage rises above 4.2 V (typical

rising threshold), a soft start initiates for each enabled channel.

POWER-GOOD FUNCTION

The ADP5056 includes an open-drain, power-good output

(PWRGD pin) that becomes active high when the three buck

regulators are operating normally. The PWRGD pin monitors

the output voltage on three channels.

A logic high of the PWRGD signal indicates that the regulated

output voltage of the buck regulator is above 95% (typical) and

below 105% (typical) of the nominal output. When the regulated

output voltage of the buck regulator falls below 93% (typical) or

rises above 107% (typical) of the nominal output for a deglitched

time greater than approximately four switching cycles, the

PWRGD pin is set to 0.

The output of the PWRGD pin is the logical AND of the internal

PWRGD signals on all channels. The output of the PWRGD pin

becomes high after the tSET delay and is 2.6 ms when the CFG2

pin is connected to ground. The tSET timer can be increased by

8× using the CFG2 pin configuration. If one internal PWRGD

signal fails, the PWRGD pin goes low with no delay.

CH1 2.0V

CH2 500mV

20.0M

M2.00ms

A CH1

440mV

20.0M

Ω

Ω BW

CH3 1.0V

Figure 44. Power-Good Delay, VIN = 12 V, VOUT = 1.0 V, fSW = 600 kHz, FPWM

Mode, Channel 1 = EN, Channel 2 = VOUT, Channel 3 = PWRGD

POWER-UP AT HIGH TEMPERATURE

Although the maximum operating junction temperature is

150°C, the ADP5056 has a lower temperature protection limit

of 125°C by which the device must be powered up. This 125°C

limit protects the internal nonvolatile memory, which is read on

this initial power-up. Power-up is the condition of VBIAS rising

above UVLOVBIAS. If power-up is attempted above 125°C, the

devices does not allow operation until the temperature drops

below 125°C. When this temperature is achieved and stored in

the volatile memory, the device is ready for normal operation

without the 125°C limit.

THERMAL SHUTDOWN

If the ADP5056 junction temperature exceeds 175°C, the thermal

shutdown circuit turns off the IC, except for the internal linear

regulators. The ADP5056 turns off the low-side MOSFET only

after the inductor current reaches zero. Extreme junction

temperatures can be the result of high current operation, poor

circuit board design, or high ambient temperature. A 15°C

hysteresis is included so that the ADP5056 does not return to

operation after thermal shutdown until the on-chip temperature

falls below 160°C. When the device exits thermal shutdown, a soft

start is initiated for each enabled channel.

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