MPC8544EBVTARGA datasheet(11/117 Pages) NXP

11 / 117 page

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8544E.

Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD/BVDD/TVDD

The core voltage must always be provided at nominal 1.0 V (see Table 2 for actual recommended core

voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must

be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the

associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy

appropriate LVCMOS type specifications. The DDR2 SDRAM interface uses a single-ended differential

receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for

the SSTL2 electrical signaling standard.

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

B/G/L/OVDD + 20%

B/G/L/OVDD

B/G/L/OVDD + 5%

of tCLOCK

1. tCLOCK refers to the clock period associated with the respective interface:

VIH

VIL

Notes:

2. Please note that with the PCI overshoot allowed (as specified above), the device

does not fully comply with the maximum AC ratings and device protection

guideline outlined in Section 4.2.2.3 of the PCI 2.2 Local Bus Specifications.

For I2C and JTAG, tCLOCK references SYSCLK.

For DDR, tCLOCK references MCLK.

For eTSEC, tCLOCK references EC_GTX_CLK125.

For LBIU, tCLOCK references LCLK.

For PCI, tCLOCK references PCI_CLK or SYSCLK.

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