MPC8560CPX667JC datasheet(52/108 Pages) NXP

52 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2

Freescale Semiconductor

I2C

Figure 35 provides the test access port timing diagram.

Figure 35. Test Access Port Timing Diagram

11 I2C

This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8560.

11.1 I2C DC Electrical Characteristics

Table 40 provides the DC electrical characteristics for the I2C interface of the MPC8560.

Table 40. I2C DC Electrical Characteristics

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

VIH

0.7

× OVDD

OVDD+ 0.3

—

Input low voltage level

VIL

–0.3

0.3

× OVDD

V—

Low level output voltage

VOL

00.2

× OVDD

Pulse width of spikes which must be suppressed

by the input filter

tI2KHKL

050

Input current each I/O pin (input voltage is

between 0.1

× OVDD and 0.9 × OVDD(max)

–10

μA3

Capacitance for each I/O pin

—10

—

Notes:

1.Output voltage (open drain or open collector) condition = 3 mA sink current.

2.Refer to the MPC8560 PowerQUICC III Integrated Communications Processor Preliminary Reference Manual for

information on the digital filter used.

3.I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.

VM = Midpoint Voltage (OVDD/2)

tJTIVKH

tJTIXKH

JTAG

External Clock

Output Data Valid

tJTKLOX

tJTKLOZ

tJTKLOV

Input

Data Valid

Output Data Valid

TDI, TMS

TDO

MPC8560CPX667JC Folha de dados(PDF) 52 Page - NXP Semiconductors

MPC8560CPX667JC Folha de dados(HTML) 52 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL