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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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DLPS024 Folha de dados(PDF) 5 Page - Texas Instruments |
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DLPS024 Folha de dados(HTML) 5 Page - Texas Instruments |
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5 / 21 page  Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. VCCO2 C6 P Positive supply voltage connected to the output voltage drivers and internal buffers. CF D1 I Configuration pin. The CF pin must be pulled High using an external 4.7-kΩ pull-up to VCCO. Selects serial mode configuration. CEO D2 — Do Not Connect. Leave unconnected. DNC D3 — Do Not Connect. Leave unconnected. DNC D4 — Do Not Connect. Leave unconnected. D3 D5 — Do Not Connect. Leave unconnected. VCCO4 D6 P Positive supply voltage connected to the output voltage drivers and internal buffers. VCCINT2 E1 P Positive 1.8-V supply voltage for internal logic. TMS E2 I JTAG Mode Select Input. TMS has an internal 50-kΩ resistive pull-up to VCCJ. DNC E3 — Do Not Connect. Leave unconnected. DNC E4 — Do Not Connect. Leave unconnected. DNC E5 — Do Not Connect. Leave unconnected. TDO E6 O JTAG Serial Data Output. TDO has an internal 50-kΩ resistive pull-up to VCCJ. GND F1 G Ground DNC F2 — Do Not Connect. Leave unconnected. DNC F3 — Do Not Connect. Leave unconnected. DNC F4 — Do Not Connect. Leave unconnected. GND F5 G Ground GND F6 G Ground TDI G1 I JTAG Serial Data Input. TDI has an internal 50k-Ω resistive pull-up to VCCJ. DNC G2 — Do Not Connect. Leave unconnected. REV_SEL0 G3 I Revision Select [1:0] Inputs. When the EN_EXT_SEL is Low, the Revision Select pins are used to select the design revision to be enabled. The Revision Select [1:0] inputs have an internal 50-kΩ resistive pull-up to VCCO. The REV_SEL0 pin must be pulled Low using an external 4.7-kΩ pull-down to Ground. The REV_SEL1 pin must be pulled Low using an external 4.7-kΩ pull-down to Ground. REV_SEL1 G4 I VCCO3 G5 P Positive supply voltage connected to the output voltage drivers and internal buffers. VCCINT3 G6 P Positive 1.8-V supply voltage for internal logic. GND H1 G Ground VCCJ H2 P Positive 2.5-V JTAG I/O supply voltage connected to the TDO output voltage driver and TCK, TMS and TDI input buffers. TCK H3 I JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. EN_EXT_SEL H4 I External Selection Input. EN_EXT_SEL has an internal 50-kΩ resistive pull- up to VCCO. The EN_EXT_SEL pin must be connected to Ground. D1 H5 — Do Not Connect. Leave unconnected. D0 H6 O DATA output pin to provide data for configuring the DLPC410ZYR in serial mode. (1) P = Power, G = Ground, I = Input, O = Output www.ti.com DLPR410 DLPS027G – AUGUST 2012 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DLPR410 |
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