DLPA2000 datasheet(32/63 Pages) TI

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Table 7-3. Additional DLPC34xx SPI Flash Requirements

FEATURE

DLPC34xx REQUIREMENT

SPI interface width

Single

SPI polarity and phase settings

SPI mode 0

Fast READ addressing

Auto-incrementing

Programming mode

Page mode

Page size

256 B

Sector size

4-KB sector

Block size

Any

Block protection bits

0 = Disabled

Status register bit(0)

Write in progress (WIP), also called flash busy

Status register bit(1)

Write enable latch (WEN)

Status register bits(6:2)

A value of 0 disables programming protection

Status register bit(7)

Status register write protect (SRWP)

Status register bits(15:8)

(that is expansion status byte)

Because the DLPC34xx controller supports only single-byte status register R/W command execution,

it may not be compatible with flash devices that contain an expansion status byte. However, as long

as the expansion status byte is considered optional in the byte 3 position and any write protection

control in this expansion status byte defaults to unprotected, then the flash device is likely compatible

with the DLPC34xx.

The DLPC34xx controller is intended to support flash devices with program protection defaults of either enabled

or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as

part of the boot process.

The DLPC34xx issues these commands during the boot process:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8

bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC34xx controller issues similar commands:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, the program or erase instruction

Note that the flash device automatically clears the write enable status after each program and erase instruction.

Table 7-4 and Table 7-5 below list the specific instruction OpCode and timing compatibility requirements. The

DLPC34xx controller does not adapt protocol or clock rate based on the flash type connected.

DLPC3420

DLPS232 – OCTOBER 2021

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