ZL30262LDF1 datasheet(59/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

ASCR

APLL Spread Spectrum Configuration Register 1

116h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

CNTEN[1:0]

DWNEN

SSEN

SPRDSS[2:0]

Default

Bits 6 to 5: Count Enable (CNTEN[1:0]). This field can be used to specify a count, or divide, value to divide the

APLL feedback divider clock down as needed for clocking the spread-spectrum logic when doing spread-spectrum

modulation in the fractional output divider. See section 5.5.8.2.

Bit 4: Spread Spectrum Down Only (DWNEN). Spread spectrum frequency modulation can be either center-spread

or down-spread. See section 5.5.8.

0 = Center-spread

1 = Down-spread

Bit 3: Spread Spectrum Enable (SSEN). When SPRDSS (see below) is set to 000, this bit enables spread spectrum

modulation in the APLL. See section 5.5.8.

Bits 2 to 0: Spread Spectrum Enable Source Select (SPRDSS[2:0]). This field specifies the APLL spread

spectrum enable control signal. See section 5.5.8.

000 = SSEN bit

001 = GPIO0

010 = GPIO1

011 = GPIO2

100 = GPIO3

101 to 111 = {unused values}

ASCNT1

APLL Spread Spectrum Count Register 1

117h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

ASCNT[7:0]

Default

Bits 7 to 0: APLL Spread-Spectrum Count (ASCNT[7:0]). The full 16-bit ASCNT[15:0] register spans this register

and ASCNT2. ASCNT is an unsigned integer that specifies the number of cycles

of the APLL’s input clock that the

device increments the output frequency and then the number of cycles that the device decrements the output

frequency. See section 5.5.8.

ASCNT2

APLL Spread Spectrum Count Register 1

118h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

ASCNT[15:8]

Default

Bits 7 to 0: APLL Spread-Spectrum Count (ASCNT[15:8]). See the ASCNT1 register description.

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