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ZL30262LDF1 Folha de dados(PDF) 46 Page - Microchip Technology

Nome de Peças ZL30262LDF1
Descrição Electrónicos  1-APLL, 6- or 10-Output Any-to-Any Clock Multiplier and Frequency Synthesizer
PDF  94 Pages
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Fabricante Electrônico  MICROCHIP [Microchip Technology]
Página de início  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

ZL30262LDF1 Folha de dados(HTML) 46 Page - Microchip Technology

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ZL30260-ZL30263
Data Sheet
46
© 2021 Microchip Technology Inc.
DS20006554A
Register Name:
ICISR
Register Description:
Input Clock Interrupt Status Register
Register Address:
44h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
—
—
—
—
XA
IC3
IC2
IC1
Default
0
0
0
0
0
0
0
0
Bit 3: XA Input Interrupt Status (XA). This bit indicates the current status of the interrupt sources for XA. This bit
is set when latched status XASR.XAL is set and the associated interrupt enable bit is also set. See section 5.8.
Bit 2 to 0: Input Clock x Interrupt Status (IC[3:1]). Each bit indicates the current status of the interrupt sources for
the corresponding input. It is set when latched status ICxSR.ICVL is set and the associated interrupt enable bit is
also set. See section 5.8.
Register Name:
OCISR1
Register Description:
Output Clock Interrupt Status Register 1
Register Address:
45h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
OC8
OC7
OC6
OC5
OC4
OC3
OC2
OC1
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Output Clock x Interrupt Status (OC[8:1]). Each bit indicates the current status of the interrupt sources
for the corresponding output. It is set when any latched status bit in the OCxSR register is set and the associated
interrupt enable bit is also set. See section 5.8.
Register Name:
OCISR2
Register Description:
Output Clock Interrupt Status Register 2
Register Address:
46h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
—
—
—
—
—
—
OC10
OC9
Default
0
0
0
0
0
0
0
0
See the OCISR1 register description above.
Register Name:
APLLISR
Register Description:
APLL Interrupt Status Register
Register Address:
47h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
—
—
—
—
—
—
—
APLL
Default
0
0
0
0
0
0
0
0
Bit 0: APLL Interrupt Status (APLL). This bit indicates the current status of the interrupt sources for the APLL. It is
set when any latched status bit in the APLLSR register is set and the associated interrupt enable bit is also set. See
section 5.8.



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