IMX6SDLCEC datasheet(95/169 Pages) NXP

95 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

4.11.10.2.2 Gated Clock Mode

The IPUx_CSIx_VSYNC, IPUx_CSIx_HSYNC, and IPUx_CSIx_PIX_CLK signals are used in this

mode. See Figure 60.

Figure 60. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on IPUx_CSIx_VSYNC (all the timings correspond to straight polarity

of the corresponding signals). Then IPUx_CSIx_HSYNC goes to high and hold for the entire line. Pixel

clock is valid as long as IPUx_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel

clocks. IPUx_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI

stops receiving data from the stream. For the next line, the IPUx_CSIx_HSYNC timing repeats. For the

next frame, the IPUx_CSIx_VSYNC timing repeats.

4.11.10.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.11.10.2.2, “Gated Clock Mode,”)

except for the IPUx_CSIx_HSYNC signal, which is not used (see Figure 61). All incoming pixel clocks

are valid and cause data to be latched into the input FIFO. The IPUx_CSIx_PIX_CLK signal is inactive

(states low) until valid data is going to be transmitted over the bus.

Figure 61. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 61 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered

IPUx_CSIx_VSYNC; active-high/low IPUx_CSIx_HSYNC; and rising/falling-edge triggered

IPUx_CSIx_PIX_CLK.

IPUx_CSIx_VSYNC

IPUx_CSIx_PIX_CLK

IPUx_CSIx_DATA_EN[19:0]

invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Start of Frame

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