PLL702-01

Clock Generator for PowerPC Based Applications

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 07/18/05 Page 5

VDD Power Up Ramp requirements:

At startup, the chip reads a lot of settings for operation according to the application’s requirements. Since reading the settings is

done only at startup and then frozen for the time of operation, it is important that the power-up environment is somewhat

controlled to facilitate proper reading of the settings. The important VDD pins are VDD_ANA and VDD_DIG and they should

apply to the following two-startup requirements:

1. VDD_DIG should be equally fast or slower than VDD_ANA. VDD_DIG performs a chip reset when VDD has reached a

certain level and VDD_ANA should have reached at least up to the same level as well to properly process the reset.

2. The VDD Power Up Ramp of VDD_DIG and VDD_ANA should pass through the section 1.8V to 2.5V no faster than 100µs

and with a continuously increasing slope. In this section the tri-level select inputs are read.

3. After VDD Power off, VDD should be allowed to go to 0V and stay there for at least 1ms before a new VDD Power on. It is

important that proper preconditions exist at every startup. Remaining charges in the chip or in circuit filter capacitors may

interfere with the preconditions so it is important that VDD has been at 0V for some time before each startup.

GND (0V)

3.3V

No limit

Min 1ms

VDD off

VDD on

2.97V

2.5V

2.2V

Min 1s

Reset enable

Reset disable

1.8V

>100us